HS9-82C85RH-8 INTERSIL [Intersil Corporation], HS9-82C85RH-8 Datasheet - Page 8

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HS9-82C85RH-8

Manufacturer Part Number
HS9-82C85RH-8
Description
Radiation Hardened CMOS Static Clock Controller/Generator
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
Waveforms
NOTE: CLK, CLK50, PCLK remain in the high state until RES goes high and 8192 valid oscillator cycles have been registered by the HS-82C85RH
internal counter t
of 16 CLK cycles (t
NOTE: If t
SFPC
EFI OR OSC
SLO/FST
EFI OR OSC
CLK50
is not met on one edge of PCLK, SLO/FST will be recognized on the next edge of PCLK.
PCLK
OST
CLK
SLO/FST
RST
(Continued)
CLK50
PCLK
time period). After RES goes high and CLK, CLK50, PCLK become active, the RESET output will remain high for a minimum
CLK
).
RESET
t
(NOTE)
SFPC
OSC
RES
CLK
STARTUP
TIME
8
OSC
FIGURE 8. RESET TIMING OSCILLATOR STOPPED (F/C LOW)
195 EFI OR OSC CYCLES
FIGURE 10. FAST TO SLOW CLOCK MODE TRANSITION
CYCLES
t
OST
8192
t
t
SHSL
SFPC
FIGURE 9. SLO/FST TIMING OVERVIEW
(NOTE)
HS-82C85RH
t
RST
t
CLIL

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