GS82032A ETC1 [List of Unclassifed Manufacturers], GS82032A Datasheet - Page 14

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GS82032A

Manufacturer Part Number
GS82032A
Description
2M Synchronous Burst SRAM
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet

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Rev: 1.03 2/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
DQ
Write Cycle Timing
A
B
ADSC
ADSP
A
- DQ
A
ADV
0
- B
GW
BW
-An
CK
E
E
E
G
D
D
1
2
3
Hi-Z
Single Write
tS tH
tS tH
tS tH
tS tH
tS tH
WR1
tS tH
ADV must be inactive for ADSP Write
tS tH
tS tH
tS tH
tS tH
tS tH
WR1
WR1
D1
A
E
2
and E
WR2
t
KH
3
Write specified byte for 2
14/23
only sampled with ADSP or ADSC
t
KL
WR2
WR2
Burst Write
D2
A
tKC
D2
ADSP is blocked by E
E
B
1
masks ADSP
D2
GS820E32T/Q-150/138/133/117/100/66
A
and all bytes for 2
C
D2
D
Write
ADSC initiated write
1
inactive
WR3
WR3
WR3
D3
B
© 1999, Giga Semiconductor, Inc.
, 2
A
Deselected with E
C
& 2
D
Deselected
2
D

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