GS820H32A2T-138 GSI [GSI Technology], GS820H32A2T-138 Datasheet - Page 14
![no-image](/images/no-image-200.jpg)
GS820H32A2T-138
Manufacturer Part Number
GS820H32A2T-138
Description
64K x 32 2M Synchronous Burst SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS820H32A2T-138.pdf
(23 pages)
- Current page: 14 of 23
- Download datasheet (345Kb)
Rev: 1.04 3/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
DQ
Write Cycle Timing
A
B
ADSC
ADSP
A
- DQ
A
ADV
0
- B
GW
BW
-An
CK
E
E
E
G
D
D
1
2
3
Hi-Z
Single Write
tS tH
tS tH
tS tH
tS tH
tS tH
WR1
tS tH
ADV must be inactive for ADSP Write
tS tH
tS tH
tS tH
tS tH
tS tH
WR1
WR1
D1
A
E
2
and E
WR2
t
KH
3
Write specified byte for 2
14/23
only sampled with ADSP or ADSC
t
KL
WR2
WR2
Burst Write
D2
A
tKC
D2
ADSP is blocked by E
E
B
1
masks ADSP
GS820H32AT/Q-150/138/133/117/100/66
D2
A
and all bytes for 2
C
D2
D
Write
ADSC initiated write
1
inactive
WR3
WR3
WR3
D3
B
© 2000, Giga Semiconductor, Inc.
, 2
A
Deselected with E
C
& 2
D
Deselected
2
E
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