GS820H32Q-4I GSI [GSI Technology], GS820H32Q-4I Datasheet - Page 18
![no-image](/images/no-image-200.jpg)
GS820H32Q-4I
Manufacturer Part Number
GS820H32Q-4I
Description
64K x 32 2M Synchronous Burst SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS820H32Q-4I.pdf
(23 pages)
- Current page: 18 of 23
- Download datasheet (345Kb)
Rev: 1.03 2/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Pipelined SCD Read - Write Cycle Timing
DQa - DQd
B
A
ADSC
A
ADSP
- BW
0
ADV
-An
GW
BW
CK
E
E
E
G
1
2
3
D
Hi-Z
tS tH
tS
tS tH
tS
tS
RD1
tH
tH
tH
Single Read
tS tH
tS tH
tS
tKQ
tOE
E2 and E3 only sampled with ADSP and ADSC
Q1
tKH
tOHZ
A
tKL
18/23
tH
Single Write
tKC
tS tH
tS tH
tS tH
D1
WR1
WR1
A
RD2
ADSC initiated read
ADSP is blocked by E inactive
GS820H32T/Q-150/138/133/117/100/66
E1 masks ADSP
Q2
Burst Read
A
© 1999, Giga Semiconductor, Inc.
Deselected with E3
Q2
B
Q2
C
Q2
D
D
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