STi7108ZWA STMICROELECTRONICS [STMicroelectronics], STi7108ZWA Datasheet - Page 3

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STi7108ZWA

Manufacturer Part Number
STi7108ZWA
Description
Advanced HD AVC decoder with 3D graphics acceleration
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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STi7108
1.1
STi7108 features summary
CPUs
2D Graphics acceleration
3D Graphics acceleration
Applications CPU, ST40-300, dual-issue, MMU, 32KI, 32KD caches, 500 MHz
delivering >900DMIPs:
Real-time CPU for a/v real-time control and network processing offload - ST40-300,
dual-issue, MMU, 32KI, 32KD caches, 500 MHz delivering >900DMIPs
Additional ST231 CPU available for further offloading of the applications CPU with
multimedia, security and networking tasks
Link list based, multi-operator 2D graphics blitter
Supports rendering, formatting and pre-composition of 2D graphics and 3D-like user
interface effects
Up to 266 Mpixels/sec with destination alpha blending
Tile RAM memory bandwidth saver accelerates blitter based pre-composition of virtual
graphics planes before display
Support for concurrent blitter use by applications and composition threads
True 3D graphics and 2D vector graphics acceleration engine (GPU), optimized for
consumer applications
Programmable Vertex (Geometry) processor and Fragment (Pixel) processor:
Compatible with industry standard APIs, OpenGL ES 1.1/2.0 and Open VG 1.0/1.1
Rendering performance up to either 720p60 with 4×FSAA or 1080i60 with 4×FSAA
(without lighting) with simple pixel shaders, and up to 720p30 with 4×FSAA with
complex pixel shaders (with lighting)
Includes an L2 cache, 256KB, 2-way set associative
Includes a tightly coupled vector FPU to accelerate 3D graphics transformations
Accelerated four times full scene anti-aliasing (4×FSAA)
Tile based for memory bandwidth efficiency
Supports decoded video as textures
Doc ID 16790 Rev 1
Introduction
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