GS88132AD-133 GSI [GSI Technology], GS88132AD-133 Datasheet - Page 10
GS88132AD-133
Manufacturer Part Number
GS88132AD-133
Description
512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS88132AD-133.pdf
(36 pages)
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Mode Pin Functions
Note:
There is a pull-up device onthe FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.04 3/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
1st address
3rd address
4th address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
11
00
10
00
01
11
11
00
01
10
Pin Name
10/36
LBO
ZZ
FT
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
GS88118A(T/D)/GS88132A(D)/GS88136A(T/D)
2nd address
1st address
3rd address
4th address
H or NC
L or NC
State
H
H
L
L
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
Standby, I
Interleaved Burst
Flow Through
Linear Burst
Function
Pipeline
Active
10
00
01
11
DD
© 2001, GSI Technology
= I
SB
11
10
01
00
BPR 1999.05.18
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