GS88132BD-150 GSI [GSI Technology], GS88132BD-150 Datasheet
GS88132BD-150
Related parts for GS88132BD-150
GS88132BD-150 Summary of contents
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... SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers ...
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DDQ ...
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DDQ ...
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DQP DDQ ...
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TQFP Pin Description Symbol Type I — ...
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Bump BGA—x18 Commom I/O—Top View (Package DDQ D NC DQB V DDQ E NC DQB V DDQ F NC DQB V DDQ G ...
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Bump BGA—x32 Common I/O—Top View DDQ D DQC DQC V DDQ E DQC DQC V DDQ F DQC DQC V DDQ G DQC DQC ...
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Bump BGA—x36 Common I/O—Top View DQPC NC V DDQ D DQC DQC V DDQ E DQC DQC V DDQ F DQC DQC V DDQ G DQC DQC ...
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BGA Pin Description Symbol Type I — ...
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GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) Block Diagram Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only ...
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Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Note: There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and ...
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Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...
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Synchronous Truth Table Address Operation Used Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst External Read Cycle, Begin Burst External Write Cycle, Begin Burst External Read Cycle, Continue Burst Read Cycle, Continue ...
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Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B that ADSP is tied ...
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Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles ...
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Absolute Maximum Ratings (All voltages reference Symbol Voltage in V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...
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V Range Logic Levels DDQ3 Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...
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Undershoot Measurement and Timing 50% V – 2 50% tKC Capacitance 2 Parameter Input Capacitance Input/Output Capacitance Note: ...
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DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 1.05 11/2005 Specifications cited are subject to change without notice. For latest documentation see ...
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Operating Currents Parameter Test Conditions (x32/ x36) Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open (x18) Standby ZZ ≥ V – 0.2 V — DD Current Device Deselected; Deselect All other inputs — ...
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AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to ...
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Begin Read A Cont Single Read Single Read CK ADSP tS tH ADSC tS ADV tS tH A0– Ba– tOE DQa–DQd Rev: 1.05 11/2005 Specifications cited ...
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Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tS tH ADV tS tH A0– Ba– and E3 only sampled with ADSC tOE ...
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... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. ...
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JTAG Port Registers JTAG Pin Descriptions Pin Pin Name I/O Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate TCK Test Clock In from the falling edge of TCK. The TMS ...
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TDI TMS TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded ...
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Tap Controller Instruction Set ID Register Contents Die Revision Code Bit # ...
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Test Logic Reset 1 0 Run Test Idle 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to ...
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Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the ...
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JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. JTAG TAP Instruction Set ...
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... OLJ –100 uA OHJC +100 uA OLJC TCK TDI TMS TDO Parallel SRAM input Rev: 1.05 11/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) Symbol V IHJ3 V ILJ3 V IHJ2 V ILJ2 I INHJ I INLJ ...
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JTAG Port AC Electrical Characteristics Parameter Symbol TCK Cycle Time tTKC TCK Low to TDO Valid tTKQ TCK High Pulse Width tTKH TCK Low Pulse Width tTKL TDI & TMS Set Up Time tTS TDI & TMS Hold Time tTH ...
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TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...
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Package Dimensions—165-Bump FPBGA (Package D) A1 CORNER TOP VIEW SEATING PLANE C Rev: 1.05 ...
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Ordering Information for GSI Synchronous Burst RAMs 1 Org Part Number 512K x 18 GS88118BT-333 512K x 18 GS88118BT-300 512K x 18 GS88118BT-250 512K x 18 GS88118BT-200 512K x 18 GS88118BT-150 256K x 32 GS88136BT-333 256K x 32 GS88132BT-300 256K ...
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Ordering Information for GSI Synchronous Burst RAMs (Continued) 1 Org Part Number 256K x 36 GS88136BT-150I 512K x 18 GS88118BGT-333 512K x 18 GS88118BGT-300 512K x 18 GS88118BGT-250 512K x 18 GS88118BGT-200 512K x 18 GS88118BGT-150 256K x 32 GS88136BGT-333 ...
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... GS88118BD-250I 512K x 18 GS88118BD-200I 512K x 18 GS88118BD-150I 256K x 32 GS88132BD-333I 256K x 32 GS88132BD-300I 256K x 32 GS88132BD-250I 256K x 32 GS88132BD-200I 256K x 32 GS88132BD-150I 256K x 36 GS88136BD-333I 256K x 36 GS88136BD-300I 256K x 36 GS88136BD-250I 256K x 36 GS88136BD-200I 256K x 36 GS88136BD-150I 512K x 18 GS88118BGD-333 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “ ...
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Ordering Information for GSI Synchronous Burst RAMs (Continued) 1 Org Part Number 512K x 18 GS88118BGD-300 512K x 18 GS88118BGD-250 512K x 18 GS88118BGD-200 512K x 18 GS88118BGD-150 256K x 32 GS88132BGD-333 256K x 32 GS88132BGD-300 256K x 32 GS88132BGD-250 ...
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... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 88118B_r1 88118B_r1; 88118B_r1_01 88118B_r1_01; 88118B_r1_02 88118B_r1_02; 88118B_r1_03 88118B_r1_03; 88118B_r1_04 88118B_r1_04; 88118B_r1_05 Rev: 1.05 11/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88118B(T/D)/GS88132B(T/D)/GS88136B(T/D) • ...