GS8321Z18E GSI [GSI Technology], GS8321Z18E Datasheet - Page 5

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GS8321Z18E

Manufacturer Part Number
GS8321Z18E
Description
36Mb Pipelined and Flow Through Synchronous NBT SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
GS8321Z18/32/36E 165-Bump BGA Pin Description
Rev: 1.06b 2/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
B
A
Symbol
, B
A
V
MCH
CKE
ADV
TMS
TDO
DQ
DQ
DQ
DQ
LBO
TCK
V
TDI
V
B
0
NC
CK
An
ZZ
E
E
E
FT
DDQ
W
G
, B
, A
DD
SS
1
3
2
A
B
C
D
1
C
, B
D
Type
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Byte Write Enable for DQ
5/34
Address field LSBs and Address Counter Preset Inputs
Burst address counter advance enable; active high
Flow Through / Pipeline Mode Control
Linear Burst Order mode; active low
Sleep mode control; active high
Clock Input Signal; active high
Data Input and Output pins
Output driver power supply
Output Enable; active low
Clock Enable; active low
Chip Enable; active high
GS8321Z18/32/36E-250/225/200/166/150/133
Write Enable; active low
Chip Enable; active low
Chip Enable; active low
Scan Test Mode Select
I/O and Core Ground
Scan Test Data Out
Must Connect High
Core power supply
Scan Test Data In
Scan Test Clock
Address Inputs
Description
No Connect
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
© 2003, GSI Technology

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