HYS64V4200GU-10 SIEMENS [Siemens Semiconductor Group], HYS64V4200GU-10 Datasheet - Page 10

• Manufacturer Part Number: HYS64V4200GU-10
• Description: 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Notes:
1. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8 and
2. These parameters are measured with continous data stream during read access and all DQ
3. All AC characteristics are shown for device level.
4. AC timing tests have V
5. If clock rising time is longer than 1ns, a time (t
6. Rated at 1.5 V
7. If t
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
10.Referenced to the time which the output achieves the open circuit condition, not to output voltage
Semiconductor Group
-8B and at 66 MHz for -10 modules. Input signals are changed once during tck, excepts for ICC6
and for standby currents when tck=infinity. All values are shown per memory component.
toggling. CL=3 and BL=4 assumed and the VDDQ current is excluded.
An initial pause of 100 s is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
point. The transition time is measured between V
with the AC output load circuit show. Specified tac and toh parameters are measured with a 50
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between
0.8V and 2.0 V.
commands must be given to “wake-up“ the device.
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
levels.
T
is longen than 1 ns, a time (t
OUTPUT
CLOCK
INPUT
tSETUP
tHOLD
tLZ
il
= 0.4 V and V
tAC
1.4V
tCL
T
-1) ns has to be added to this parameter.
tCH
tOH
ih
= 2.4 V with the timing referenced to the 1.4 V crossover
tAC
t
tHZ
T
2.4 V
0.4 V
fig.1
10
T
/2 -0.5) ns has to be added to this parameter.
ih
and V
1.4V
il
. All AC measurements assume t
I/O
HYS64(72)V4200/8220GU
Measurement conditions for
I/O
Z=50 Ohm
tac and toh
SDRAM-Modules
50 pF
+ 1.4 V
50 Ohm
50 pF
T
=1ns