GS881Z18AT GSI [GSI Technology], GS881Z18AT Datasheet
GS881Z18AT
Related parts for GS881Z18AT
GS881Z18AT Summary of contents
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... For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock ...
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... DDQ Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 GS881Z18AT Pinout (Package T) 512K x 18 Top View 2/ ...
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DQP DDQ ...
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TQFP Pin Descriptions Symbol Type ...
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... GS881Z18/36A NBT SRAM Functional Block Diagram Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 Amps Sense Drivers Write 5/31 © 2001, GSI Technology ...
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... B C with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock ...
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... Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. ...
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Pipelined and Flow Through Read Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition ...
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Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.03 11/2004 Specifications cited are subject to change without notice. ...
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B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see ...
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... SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode ...
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... During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. ...
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Absolute Maximum Ratings (All voltages reference Symbol DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O Pin OUT P ...
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V Range Logic Levels DDQ3 Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the ...
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Undershoot Measurement and Timing 50% V – 2 50% tKC Capacitance 2 Parameter Input Capacitance Input/Output Capacitance Note: ...
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DC Electrical Characteristics Parameter Input Leakage Current (except mode pins) ZZ Input Current FT Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For ...
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Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 17/31 © 2001, GSI Technology ...
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AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid Pipeline Clock to Output in Low-Z Setup time Hold time Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock ...
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Write A Read CKE ADV Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation ...
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Write A Write CKE ADV A0– D(A) G *Note High(False ...
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JTAG Port Registers JTAG Pin Descriptions Pin Pin Name I/O Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate TCK Test Clock In from the falling edge of TCK. The TMS ...
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TDI TMS TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded ...
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Tap Controller Instruction Set ID Register Contents Die Revision Code Bit # ...
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Test Logic Reset 1 0 Run Test Idle 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to ...
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Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the ...
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JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. JTAG TAP Instruction Set ...
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... OHJ OLJ –100 uA OHJC +100 uA OHJC TCK TDI TMS TDO Parallel SRAM input Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 Symbol V IHJ3 V ILJ3 V IHJ V ILJ I INHJ I INLJ I ...
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JTAG Port AC Electrical Characteristics Parameter Symbol TCK Cycle Time tTKC TCK Low to TDO Valid tTKQ TCK High Pulse Width tTKH TCK Low Pulse Width tTKL TDI & TMS Set Up Time tTS TDI & TMS Hold Time tTH ...
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TQFP Package Drawing (Package T) Symbol Description Min. Nom. Max A1 Standoff 0.05 A2 Body Thickness 1.35 b Lead Width 0.20 c Lead Thickness 0.09 D Terminal Dimension 21.9 D1 Package Body 19.9 E Terminal Dimension 15.9 E1 Package Body ...
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... GS881Z36AT-200 256K x 36 GS881Z36AT-166 256K x 36 GS881Z36AT-150 256K x 36 GS881Z36AT-133 512K x 18 GS881Z18AT-250I 512K x 18 GS881Z18AT-225I 512K x 18 GS881Z18AT-200I 512K x 18 GS881Z18AT-166I 512K x 18 GS881Z18AT-150I 512K x 18 GS881Z18AT-133I 256K x 36 GS881Z36AT-250I 256K x 36 GS881Z36AT-225I 256K x 36 GS881Z36AT-200I 256K x 36 ...
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... Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; Types of Changes New Format or Content 881Z18A_r1 881Z18A_r1; 881Z18A_r1_01 881Z18A_r1_01; 881Z18A_r1_02 881Z18A_r1_02; 881Z18A_r1_03 Rev: 1.03 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS881Z18/36AT-250/225/200/166/150/133 Page;Revisions;Reason • Creation of new datasheet • ...