GS881Z18T GSI [GSI Technology], GS881Z18T Datasheet - Page 10
GS881Z18T
Manufacturer Part Number
GS881Z18T
Description
8Mb Pipelined and Flow Through Synchronous NBT SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS881Z18T.pdf
(34 pages)
- Current page: 10 of 34
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Rev: 1.10 8/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com
Pipeline Mode Data I/O State Diagram
Key
Current State (n)
Clock (CK)
Command
Intermediate
ƒ
Current State and Next State Definition for
Transition
Input Command Code
Intermediate State (N+1)
High Z
(Data In)
B W
Current State
n
D
R
Transition
ƒ
Intermediate
Next State (n+2)
10/34
n+1
B
Intermediate
Intermediate
Intermediate
D
W
State
High Z
ƒ
R
Pipeline Mode Data I/O State Diagram
Intermediate
Notes
1. The Hold command (CKE Low) is not
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
shown because it prevents any state change.
n+2
Next State
W
ƒ
D
Data Out
(Q Valid)
R
GS881Z18/36T-11/100/80/66
n+3
B
© 1998, Giga Semiconductor, Inc.
Intermediate
ƒ
Preliminary
.
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