PPC405EP-3GB133CZ AMCC [Applied Micro Circuits Corporation], PPC405EP-3GB133CZ Datasheet - Page 35

• Manufacturer Part Number: PPC405EP-3GB133CZ
• Description: PowerPC 405EP Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

PPC405EP – PowerPC 405EP Embedded Processor
Table 6. Signal Functional Description (Sheet 5 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
AMCC
System Interface
Trace Interface
Power
[RejectPkt0:1]
Signal Name
GPIO00:31
SysReset
[TrcClk]
[TS3:6]
TestEn
SysClk
[TS1E]
[TS2E]
[TS1O]
[TS2O]
SysErr
AGND
TRST
OV
AV
GND
TDO
TCK
Halt
DD
DD
Test data out.
JTAG test clock. The frequency of this input can range from DC to
25MHz.
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller.
Main system reset. External logic can drive this bidirectional pin low
(minimum of 16 cycles) to initiate a system reset. A system reset can
also be initiated by software. Implemented as an open-drain output
(two states; 0 or open circuit).
Set to 1 when a Machine Check is generated.
Halt from external debugger.
General Purpose I/O. All of the GPIO signals are multiplexed with
other signals.
Test Enable. Used only for manufacturing tests. Pull down for normal
operation.
Main system clock input.
External request to reject a packet.
Clean voltage input for the PLL.
Clean Ground input for the PLL.
Even Trace execution status. To access this function, software must
toggle a DCR bit
Odd Trace execution status. To access this function, software must
toggle a DCR bit
Trace status. To access this function, software must toggle a DCR bit
Trace interface clock. Operates at half the CPU core frequency. To
access this function, software must toggle a DCR bit
Ground
Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also
Output driver voltage—3.3V.
thermal balls.
Description
Revision 1.07 – September 10, 2007
I/O
I/O
I/O
na
na
O
O
O
O
O
O
I
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
1.8V CMOS
w/pull-down
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
Type
na
na
Data Sheet
Notes
1, 4
1, 2
1, 2
na
na
5
6
1
1
1
1
1
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