PPC405GP-3BE133C AMCC [Applied Micro Circuits Corporation], PPC405GP-3BE133C Datasheet - Page 55

• Manufacturer Part Number: PPC405GP-3BE133C
• Description: Power PC 405GP Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

Revision 2.03 – September 7, 2007
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to
enable default initial conditions prior to PPC405GP start-up. The actual capture instant is the nearest SysClk edge
before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. The recommended pull-up is 3kΩ to +3.3V or 10kΩ to
+5V. The recommended pull-down is 1KΩ to GND. These pins are use for strap functions only during reset. They
are used for other signals during normal operation. The following table lists the strapping pins along with their
functions and strapping options. The pin for the 456-ball package is listed first (for example, AF3), followed by the
corresponding pin for the 413-ball package (for example, U8), which appears as AF3/U8. The signal names
assigned to the pins for normal operation follow the pin numbers.
AMCC
PPC405GP Strapping Pin Assignments
PLL Tuning
for 6
for 7 < M
for 12 < M
PLL Forward Divider
PLL Feedback Divider
PLB Divider from CPU
OPB Divider from PLB
≤
M
≤
≤
≤
Data Sheet
1
12 use choice 5
32 use choice 6
7 use choice 3
Function
2
2
2
2
Choice 1; TUNE[5:0] = 010001
Choice 2; TUNE[5:0] = 111011
Choice 3; TUNE[5:0] = 010011
Choice 4; TUNE[5:0] = 111101
Choice 5; TUNE[5:0] = 010101
Choice 6; TUNE[5:0] = 010110
Choice 7; TUNE[5:0] = 111110
Choice 8; TUNE[5:0] = 100100
Bypass mode
(Part 1 of 2)
Divide by 3
Divide by 4
Divide by 6
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 1
Divide by 2
Divide by 3
Divide by 4
405GP – Power PC 405GP Embedded Processor
Option
UART0_Tx
EMCTxD3
EMCTxD1
DMAAck0
DMAAck2
D16/A17
B14/A15
P25/R23
L25/K21
AF3/U8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Ball Strapping
UART0_DTR
EMCTxD2
EMCTxD0
DMAAck1
DMAAck3
B15/B14
L24/J22
J26/F22
AF2/T8
C12/A8
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
UART0_RTS
AD16/AB15
0
1
0
1
0
1
0
1
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