AMD-762JLC AMD [Advanced Micro Devices], AMD-762JLC Datasheet - Page 36
AMD-762JLC
Manufacturer Part Number
AMD-762JLC
Description
System Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AMD-762JLC.pdf
(122 pages)
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AMD-762™ System Controller Data Sheet
Figure 8.
24
Generator
Clock
33 MHz (for Southbridge)
33 MHz
100/133 MHz
66 MHz
66 MHz
System Clocking with 33-MHz PCI Bus
33-MHz PCI Clocks
AGP Slot
The AMD-762 system controller implements three internal
PLLs to control clock skew on-chip for the SYSCLK, AGPCLK,
and PCICLK domains. An external feedback path is required
on the motherboard for the 66-MHz PCI PLL when operating in
66-MHz mode. This requires the PCI_66CLK[0] output pin to be
connected back into the AMD-762 system controller’s PCICLK
input for skew control, as shown in Figure 7 on page 23.
These PLLs can be bypassed for motherboard testing. Refer to
Chapter 3 for further details of PLL bypass testing.
Preliminary Information
Functional Operation
PCICLK
SYSCLK
AGPCLK
AMD-762™ System Controller
AMD-766™ Peripheral
Bus Controller
Northbridge
Southbridge
32-bit, 33-MHz PCI Bus Slots
CLKOUT[1]n
CLKOUT[2]n
CLKOUT[3]n
CLKOUT[0]n
24416C—December 2001
DDR DIMMs
Chapter 2
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