RHF1201 STMICROELECTRONICS [STMicroelectronics], RHF1201 Datasheet - Page 10

• Manufacturer Part Number: RHF1201
• Description: Rad-hard 12-bit 0.5 to 50 Msps A/D converter
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Application information
7.2
7.2.1
10/18
Output enable (OEB)
When set to low level (V
When set to high level (V
converter goes on sampling. When OEB is set to a low level again, the data arrives on the
output with a very short T
Figure 3: Timing diagram on page 5
Slew rate control (SRC)
When set to high level (V
digital noise power is reduced to the minimum. When set to low level (V
are twice as fast.
Out of range (OR)
This function is implemented on the output stage in order to set an “Out of Range” flag
whenever the digital data is over the full scale range.
Typically, there is a detection of all the data at ’0’ or all the data at ’1’. It sets an output signal
OR which is in low level state (V
state (V
Data ready (DR)
The Data Ready output is an image of the clock being synchronized on the output data (D0
to D11). This is a very helpful signal that simplifies the synchronization of the measurement
equipment or of the controlling DSP.
As all other digital outputs, DR goes into high impedance state when OEB is set to high level
as shown in
Driving the analog input
Differential inputs
The RHF1201is designed to obtain optimum performance when driven on differential inputs.
An RF transformer is an efficient way of achieving this high performance.
Figure 4: Differential input configuration
the primary of the transformer, while the secondary drives both ADC inputs. The common
mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the
transformer in order to bias the input signal around this common voltage, internally set close
to 0.5V. The INCM is de-coupled to maintain a low noise level on this node. Our evaluation
board is mounted with a 1:1 ADT1-1 transformer from Minicircuits. You might also use a
higher impedance ratio (1:2 or 1:4) to reduce the driving requirement on the analog signal
source.
Each analog input can drive a 1 V
amplitude is 2 V
OH
) when the data is out of range.
Figure 3: Timing diagram on page
pp
.
IL
IH
IH
on
), all digital outputs remain active and are in low impedance state.
), all digital output buffers are in high impedance state while the
), all digital output currents are limited to a clamp value so that
delay. This mechanism allows the chip select of the device.
OL
pp
) when the data stays within the range, or in high level
summarizes this functionality.
amplitude input signal, so the resulting differential
describes the schematics. The input signal is fed to
5.
IL
), the output edges
RHF1201