RHF1201 STMICROELECTRONICS [STMicroelectronics], RHF1201 Datasheet - Page 9

• Manufacturer Part Number: RHF1201
• Description: Rad-hard 12-bit 0.5 to 50 Msps A/D converter
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

RHF1201
7
7.1
Application information
The RHF1201 is a high speed analog to digital converter based on a pipeline architecture
and a 0.25 µm CMOS process to achieve the best performance in terms of linearity and
power consumption.
The pipeline structure consists of 11 internal conversion stages in which the analog signal is
fed and sequentially converted into digital data. Signal input is sampled on the rising edge of
the clock.
The first 10 stages of the conversion include at each stage, an analog to digital converter, a
digital to analog converter, a Sample and Hold, and an amplifier with a gain of 2. A 1.5 bit
conversion resolution is also performed at each stage. The final stage is simply a
comparator. Each resulting LSB-MSB couple is then time shifted to recover from the delay
caused by the conversion. Digital data correction completes the processing by recovering
from the redundancy of the (LSB-MSB) couple at each stage. The corrected data is output
through the digital buffers.
The advantages of such a converter reside in the combination of pipeline architecture and
the most advanced technologies. The highest dynamic performances are achieved while
consumption remains at the lowest level.
RHF1201 operating modes
Extra functionalities are provided to simplify the application board as much as possible. The
operation modes offered by the RHF1201 are described in the following table.
Table 10.
Data format select (DFSB)
When set to low level (V
output MSB. This can be of interest when performing some further signal processing.
When set to high level (V
(V
(V
RANGE>
RANGE>
-RANGE
-RANGE
IN
IN
Analog input differential level
-V
-V
INB
INB
)
)
RHF1201 operating modes
(V
(V
IN
IN
-V
-V
X
X
X
>
>
>
>
INB
INB
)
)
IL
IH
(V
(V
>-RANGE
>-RANGE
), the digital input DFSB provides a two’s complement digital
Inputs
RANGE
RANGE
), DFSB provides a standard binary output coding.
IN
IN
-V
-V
INB
INB
)
)
DFSB
H
H
H
X
X
X
L
L
L
OEB
H
X
X
L
L
L
L
L
L
SRC
X
X
X
X
X
X
X
H
L
OR
HZ
H
H
H
H
X
X
L
L
Application information
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
DR
HZ
Outputs
D11 Complemented
D11 Complemented
D11 Complemented
Most significant
High slew rate
Low slew rate
bit (MSB)
D11
D11
D11
HZ
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