M366S1623ET0 SAMSUNG [Samsung semiconductor], M366S1623ET0 Datasheet - Page 11

• Manufacturer Part Number: M366S1623ET0
• Description: 16Mx64 SDRAM DIMM based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
• Manufacturer: SAMSUNG [Samsung semiconductor]

M366S1623ET0
M366S1623ET0-C75(Intel SPD 1.2B ver. base)
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Byte #
Organization : 16Mx64
Contents ;
Composition : 8Mx8 *16
Used component part # : K4S640832E-TC75
# of rows in module : 2 rows
# of banks in component : 4 banks
Feature : 1,375mil height & double sided component
Refresh : 4K/64ms
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
0
1
2
3
4
5
6
7
8
9
# of bytes written into serial memory at module manufacturer
Total # of bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module
Data width of this assembly
...... Data width of this assembly
Voltage interface standard of this assembly
SDRAM cycle time @CAS latency of 3
SDRAM access time from clock @CAS latency of 3
DIMM configuraion type
Refresh rate & type
Primary SDRAM width
Error checking SDRAM width
Minimum clock delay for back-to-back random column address
SDRAM device attributes : Burst lengths supported
SDRAM device attributes : # of
SDRAM device attributes : CAS latency
SDRAM device attributes : CS latency
SDRAM device attributes : Write latency
SDRAM module attributes
SDRAM device attributes : General
SDRAM cycle time @CAS latency of 2
SDRAM access time from clock@CAS latency of 2
SDRAM cycle time @CAS latency of 1
SDRAM access time from clock@CAS latency of 1
Minimum row precharge time (=t
Minimum row active to row active delay (t
Minimum RAS to CAS delay (=t
Minimum activate precharge time (=t
Module
Command and address signal input setup time
Command and address signal input hold time
Data signal input setup time
row
rows
density
on this assembly
Function Described
banks
RCD
RP
)
)
RAS
on SDRAM device
)
RRD
)
15.625us, support self refresh
precharge all, auto precharge
Non-buffered, non-registered
Burst Read Single bit Write
+/- 10% voltage tolerance,
& redundant addressing
Function Supported
1, 2, 4, 8 & full page
256bytes (2K-bit)
2
t
rows
CCD
Non parity
128bytes
4
SDRAM
2
64 bits
LVTTL
0 CLK
0 CLK
7.5ns
5.4ns
1.5ns
0.8ns
1.5ns
None
banks
20ns
15ns
20ns
45ns
-75
rows
12
x8
= 1CLK
9
3
-
-
-
-
-
of 64MB
PC133 Unbuffered DIMM
REV. 0.0 Dec, 2000
Hex value
0Ch
0Eh
2Dh
80h
08h
04h
09h
02h
40h
00h
01h
75h
54h
00h
80h
08h
00h
01h
8Fh
04h
04h
01h
01h
00h
00h
00h
00h
00h
14h
0Fh
14h
10h
15h
08h
15h
-75
Note
1
1
2
2
2
2