LIS302DL_07 STMICROELECTRONICS [STMicroelectronics], LIS302DL_07 Datasheet - Page 28
LIS302DL_07
Manufacturer Part Number
LIS302DL_07
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.LIS302DL_07.pdf
(42 pages)
- Current page: 28 of 42
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Register description
7.4
7.5
28/42
Table 22.
CTRL_REG3 [Interrupt CTRL register] (22h)
Table 23.
Table 24.
Table 25.
HP_FILTER_RESET (23h)
Dummy register. Reading at this address zeroes instantaneously the content of the internal
high pass-filter. If the high pass filter is enabled all three axes are instantaneously set to 0g.
This allows to overcome the settling time of the high pass filter.
IHL
PP_OD
I2CFG2
I2CFG1
I2CFG0
I1CFG2
I1CFG1
I1CFG0
IHL
I1(2)_CFG2
HP_coeff2,1
00
01
10
11
0
0
0
0
1
1
High pass filter cut-off frequency configuration.
Register
Register description
Truth table
PP_OD
Interrupt active high, low. Default value 0.
(0: active high; 1: active low)
Push-pull/Open Drain selection on interrupt pad. Default value 0.
(0: push-pull; 1: open drain)
Data Signal on Int2 pad control bits. Default value 000.
(see table below)
Data Signal on Int1 pad control bits. Default value 000.
(see table below)
I1(2)_CFG1
I2CFG2
0
0
1
1
0
1
(DR=100 Hz)
ft (Hz)
I2CFG1
0.25
0.5
2
1
I1(2)_CFG0
I2CFG0
0
1
0
1
0
1
I1CFG2
FF_WU_1 or FF_WU_2
(DR=400 Hz)
Click interrupt
Int1(2) Pad
Data ready
FF_WU_1
FF_WU_2
I1CFG1
ft (Hz)
GND
8
4
2
1
LIS302DL
I1CFG0
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