LIS3LV02DL_08 STMICROELECTRONICS [STMicroelectronics], LIS3LV02DL_08 Datasheet - Page 32

• Manufacturer Part Number: LIS3LV02DL_08
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Register description
7.9
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Table 31.
PD1, PD0 bit allows to turn the device out of power-down mode. The device is in power-
down mode when PD1, PD0= “00” (default value after boot). The device is in normal mode
when either PD1 or PD0 is set to 1.
DF1, DF0 bit allows to select the data rate at which acceleration samples are produced. The
default value is “00” which corresponds to a data-rate of 40 Hz. By changing the content of
DF1, DF0 to “01”, “10” and “11” the selected data-rate will be set respectively equal to
160 Hz, 640 Hz and to 2560 Hz.
ST bit is used to activate the self test function. When the bit is set to one, an output change
will occur to the device outputs (refer to table 2 and 3 for specification) thus allowing to
check the functionality of the whole measurement chain.
Zen bit enables the Z-axis measurement channel when set to 1. The default value is 1.
Yen bit enables the Y-axis measurement channel when set to 1. The default value is 1.
Xen bit enables the X-axis measurement channel when set to 1. The default value is 1.
CTRL_REG2 (21h)
Table 32.
Table 33.
ST
Zen
Yen
Xen
FS
BDU
BLE
BOOT
IEN
DRDY
FS
Register description (continued) (20h)
Register (21h)
Register description (21h)
BDU
Self Test Enable
(0: normal mode; 1: self-test active)
Z-axis enable
(0: axis off; 1: axis on)
Y-axis enable
(0: axis off; 1: axis on)
X-axis enable
(0: axis off; 1: axis on)
Full Scale selection
(0: ±2g; 1: ±6g)
Block Data Update
(0: continuous update; 1: output registers not updated between MSB and LSB
reading)
Big/Little Endian selection
(0: little endian; 1: big endian)
Reboot memory content
Interrupt ENable
(0: data ready on RDY pad; 1: interrupt events on RDY pad)
Enable Data-Ready generation
BLE
BOOT
IEN
DRDY
SIM
LIS3LV02DL
DAS