EMC6D100-DK SMSC [SMSC Corporation], EMC6D100-DK Datasheet - Page 23

• Manufacturer Part Number: EMC6D100-DK
• Description: ENVIRONMENTAL MONITORING AND CONTROL DEVICE WITH AUTOMATIC FAN CAPABILITY
• Manufacturer: SMSC [SMSC Corporation]

Environmental Monitoring and Control Device
Datasheet
6.4
SMSC EMC6D100/EMC6D101
conversion of each voltage and temperature reading is performed once every monitoring cycle. This is a
power saving mode.
The cycle monitoring function is started by doing a write to the Ready/Lock/Start Register, setting the Start
bit (Bit 0) high. The part then performs a “round robin” sampling of the inputs, in the order shown above.
When the cycle monitoring function is started, it cycles through each measurement in sequence, and it
performs a single conversion for each voltage and temperature approximately once every second. Each
measured value is compared to values stored in the Limit registers. When the measured value violates (or
is equal to) the programmed limit the Hardware Monitor Block will set a corresponding status bit in the
Interrupt Status Registers.
If auto fan option is selected, the hardware will adjust the operation of the fans accordingly. See section
7.4.2 Auto Fan Control Operating Mode on page 31.
The results of each sampling and conversion can be found in the Reading Registers and are available at
any time, however, they are only updated once every 1-1.4 seconds.
Interrupt Status Registers
The Hardware Monitor Block contains three interrupt status registers. These registers are used to reflect
the state of all temperature, voltage and fan violation of limit error conditions and diode fault conditions that
the Hardware Monitor Block monitors.
When an error occurs during the conversion cycle, its corresponding bit is set in its respective interrupt
status register. The bit remains set until the register is read by software, at which time the bit will be
cleared to ‘0’ if the associated error event no longer violates the limit conditions or if the diode fault
condition no longer exists. Reading the register will not cause a bit to be cleared if the source of the status
bit remains active.
These registers are read only – a write to these registers have no effect. These registers default to 0x00
on VCC POR and Initialization.
See the description of the Interrupt Status registers in section Chapter 8 Register Set.
Each interrupt event can be enabled into the interrupt status registers. See the figure below for the status
and enable bits used to control the interrupt bits and INT# pin.
DATASHEET
Page 23
Rev. 09-09-04