EMC6D103-CK SMSC [SMSC Corporation], EMC6D103-CK Datasheet - Page 75
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EMC6D103-CK
Manufacturer Part Number
EMC6D103-CK
Description
FAN CONTROL DEVICE WITH HIGH FREQUENCY PWM
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.EMC6D103-CK.pdf
(89 pages)
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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Datasheet
SMSC EMC6D103
8.2.26
8.2.27
Register
Address
Register
Address
7Eh
7Fh
Read/
Read/
Write
Write
R/W
R/W
Register 7Eh: Interrupt Enable 1 Register
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
This register is used to enable individual voltage error events to set the corresponding status bits in
the interrupt status registers. This register also contains the group voltage enable bit (Bit[0] VOLT),
which is used to enable voltage events to force the interrupt pin (INT#) low if interrupts are enabled
(see Bit[2] INTEN of the Special Function register at offset 7Ch).
This register contains the following bits:
Bit[0] Group INT# Voltage Enable (VOLT)
0=Out-of-limit voltages do not affect the state of the INT# pin (default)
1=Enable out-of-limit voltages to make the INT# pin active low
Bit[1] Reserved
Bit[2] 2.5V Error Enable
Bit[3] Vccp Error Enable
Bit[4] Reserved
Bit[5] 5V Error Enable
Bit[6] 12V Error Enable
Bit[7] VCC Error Enable
The individual voltage error event bits are defined as follows:
0=disable
1=enable.
See
Register 7Fh: Configuration Register
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register contains the following bits:
Bit[0] TACH3/INT# pin select: 0=TACH, 1=INT#
Figure 6.1 Interrupt Controlon page
Interrupt Enable 1 (Voltages)
Register Name
Configuration
Table 8.44 Register 7Eh: Interrupt Enable 1 Register
Register Name
Table 8.45 Register 7Fh: Configuration Register
(MSb)
Bit 7
INIT
(MSb)
DATASHEET
Bit 7
VCC
SMSC
Bit 6
27.
75
Bit 6
12V
SMSC
Bit 5
Bit 5
5V
SUREN
Bit 4
Bit 4
RES
TRDY
Bit 3
VCCP
Bit 3
Bit 2
RES
Bit 2
25V
P2INT
Bit 1
Bit 1
RES
Revision 0.4 (04-04-05)
T3INT
(LSb)
VOLT
(LSb)
Bit 0
Bit 0
Default
Default
Value
Value
ECh
10h
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