EMC6D103-CK SMSC [SMSC Corporation], EMC6D103-CK Datasheet - Page 81

• Manufacturer Part Number: EMC6D103-CK
• Description: FAN CONTROL DEVICE WITH HIGH FREQUENCY PWM
• Manufacturer: SMSC [SMSC Corporation]

Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Datasheet
SMSC EMC6D103
8.2.39
Register
Address
94h
95h
96h
Read/
Write
R/W
R/W
R/W
1=mode 2 – enhanced.
Bit[4] Tach (Mode 2 only)
0=Don’t ignore first 3 edges (default)
1=Ignore first 3 tachometer edges after guard time
Note: This bit has been added to support a small sampling of fans that emit irregular tach pulses
Bit[7:5] RESERVED
Read to these bits return 0, writes have no affect.
Registers 94h-96h: PWMx Option Registers
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
Bits[1:0] Tachs reading registers associated with PWMx are updated: (Mode 2 only)
00=once a second (default)
01=twice a second
1x=every 300msec
Bit[2] Snap to Zero (SZEN)
This bit determines if the PWM output ramps down to OFF or if it is immediately set to zero.
0=Step Down the PWMx output to Off at the programmed Ramp Rate
1=Transition PWMx to Off immediately when the calculated duty cycle is 00h (default)
Bit[4:3] Guard time (Mode 2 only)
00=63 clocks (90kHz clocks ~ 700usec)
01=32 clocks (90kHz clocks ~ 356usec) (default)
10=16 clocks (90kHz clocks ~ 178usec)
11=8 clocks (90kHz clocks ~ 89usec)
Bit[5] Opportunistic Mode Enable
0= Opportunistic Mode Disabled. Update Tach Reading once per PWMx Update Period (see Bits[1:0]
in this register)
1=Opportunistic Mode is Enabled. The tachometer reading register is updated any time a valid
tachometer reading can be made. If a valid reading is detected prior to the Update cycle, then the
Update counter is reset.
Bit[7:6] Reserved
when the PWM transitions ‘ON’. Typically, the guard time is sufficient for most fans.
Table 8.57 Registers 94h-96h: PWMx Option Registers
PWM1 Option
PWM2 Option
PWM3 Option
Register
Name
(MSb)
Bit 7
RES
RES
RES
DATASHEET
Bit 6
RES
RES
RES
81
Bit 5
OPP
OPP
OPP
GRD1
GRD1
GRD1
Bit 4
GRD0
GRD0
GRD0
Bit 3
SZEN
SZEN
SZEN
Bit 2
UPDT1
UPDT1
UPDT1
Bit 1
Revision 0.4 (04-04-05)
UPDT0
UPDT0
UPDT0
(LSb)
Bit 0
Default
Value
0Ch
0Ch
0Ch