EDD2516AKTA-7A ELPIDA [Elpida Memory], EDD2516AKTA-7A Datasheet - Page 39
EDD2516AKTA-7A
Manufacturer Part Number
EDD2516AKTA-7A
Description
256M bits DDR SDRAM
Manufacturer
ELPIDA [Elpida Memory]
Datasheet
1.EDD2516AKTA-7A.pdf
(49 pages)
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EDD2516AKTA
DM Control
DM can mask input data. In ×16 products, UDM and LDM can mask the upper and lower byte of input data,
respectively. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not
written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0.
t1
t2
t3
t4
t5
t6
DQS
DQ
Mask
Mask
DM
Write mask latency = 0
DM Control
Preliminary Data Sheet E0303E40 (Ver. 4.0)
39
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