HCTS00HMSR INTERSIL [Intersil Corporation], HCTS00HMSR Datasheet

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HCTS00HMSR

Manufacturer Part Number
HCTS00HMSR
Description
Radiation Hardened Quad 2-Input NAND Gate
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
1.HCTS00HMSR.pdf (9 pages)
August 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Cosmic Ray Upset Immunity < 2 x 10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• CMOS Input Compatibility Ii
Description
The Intersil HCTS00MS is a Radiation Hardened Quad 2-Input
NAND Gate. A high on both inputs forces the output to a Low
state.
The HCTS00MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS00MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS00DMSR
HCTS00KMSR
HCTS00D/
Sample
HCTS00K/
Sample
HCTS00HMSR
(Typ)
- VIL = 0.8V Max
- VIH = VCC/2 Min
NUMBER
PART
TEMPERATURE
-55
-55
o
o
RANGE
C to +125
C to +125
+25
+25
+25
10
o
o
o
C
C
C
RAD (Si)/s 20ns Pulse
|
o
o
Copyright
C
C
5 A at VOL, VOH
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
Sample
Die
SCREENING
12
o
C to +125
LEVEL
©
RAD (Si)/s
-9
Intersil Corporation 1999
Errors/Gate Day (Typ)
o
-9
C
2
14 Lead SBDIP
14 Lead Ceramic
Flatpack
14 Lead SBDIP
14 Lead Ceramic
Flatpack
Die
/mg
Errors/Bit-Day
PACKAGE
370
Pinouts
NOTE: L = Logic Level Low, H = Logic level High
Functional Diagram
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(2, 5, 10, 13)
HCTS00MS
GND
(1, 4, 9, 12)
A1
B1
A2
B2
Y1
Y2
An
H
H
An
Bn
L
L
(FLATPACK) MIL-STD-1835 CDFP3-F14
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
GND
INPUTS
A1
B1
Y1
A2
B2
Y2
MIL-STD-1835 CDIP2-T14
Quad 2-Input NAND Gate
1
2
3
4
5
6
7
TRUTH TABLE
1
2
3
4
5
6
7
TOP VIEW
TOP VIEW
Radiation Hardened
Bn
H
H
L
L
Spec Number
14
13
12
11
10
9
8
File Number
14
13
12
11
10
9
8
VCC
B4
A4
Y4
B3
A3
Y3
OUTPUTS
Yn
H
H
H
L
Yn
(3, 6, 8, 11)
518774
2139.2
VCC
B4
A4
Y4
B3
A3
Y3

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HCTS00HMSR Summary of contents

Page 1

... HCTS00KMSR - +125 C Intersil Class S Equivalent o HCTS00D/ +25 C Sample Sample o HCTS00K/ +25 C Sample Sample o HCTS00HMSR +25 C Die CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | http://www.intersil.com or 407-727-9207 Copyright HCTS00MS Pinouts 2 /mg -9 Errors/Bit-Day 12 RAD (Si)/s -9 Errors/Gate Day (Typ +125 ...

Page 2

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage ...

Page 3

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Input to Yn TPHL VCC = 4.5V VCC = 4.5V Input to Yn TPLH VCC = 4.5V VCC = 4.5V NOTES: 1. All voltages referenced to device GND measurements assume ...

Page 4

TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B ...

Page 5

TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OPEN GROUND STATIC BURN-IN I TEST CONDITIONS (Note 10, 12, 13 STATIC BURN-IN II TEST CONNECTIONS (Note ...

Page 6

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 7

AC Timing Diagrams VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL AC VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 HCTS00MS AC Load Circuit DUT TPHL CL ...

Page 8

Die Characteristics DIE DIMENSIONS mils 2.20mm x 2.24mm METALLIZATION: Type: AlSi Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND ...

Page 9

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, ...

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