HCTS08HMSR INTERSIL [Intersil Corporation], HCTS08HMSR Datasheet

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HCTS08HMSR

Manufacturer Part Number
HCTS08HMSR
Description
Radiation Hardened Quad 2-Input AND Gate
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
August 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD(Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS08MS is a Radiation Hardened Quad 2-Input
AND Gate. A high on both inputs force the output to a High state.
The HCTS08MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS08MS is supplied in a 14 lead Ceramic Flatpack
Package (K suffix) or a 14 lead SBDIP Package (D suffix).
Ordering Information
HCTS08DMSR
HCTS08KMSR
HCTS08D/
Sample
HCTS08K/
Sample
HCTS08HMSR
(Typ)
- VIL = 0.8V
- VIH = VCC/2
NUMBER
PART
TEMPERATURE
-55
-55
o
o
RANGE
C to +125
C to +125
+25
+25
+25
10
o
o
o
C
C
C
RAD(Si)/s 20ns Pulse
5 A at VOL, VOH
|
o
o
Copyright
C
C
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
Sample
Die
SCREENING
12
o
C to +125
LEVEL
©
Rads (Si)/Sec
Intersil Corporation 1999
o
-9
C
2
14 Lead SBDIP
14 Lead Ceramic
Flatpack
14 Lead SBDIP
14 Lead Ceramic
Flatpack
Die
/mg
Errors/Bit-Day
PACKAGE
1
Pinouts
NOTE: L = Logic Level Low, H = Logic level High
Functional Diagram
HCTS08MS
(2, 5, 10, 13)
GND
(1, 4, 9, 12)
A1
B1
A2
B2
Y1
Y2
An
Bn
An
H
H
L
L
FLATPACK PACKAGE (FLATPACK)
14 LEAD CERAMIC DUAL-IN-LINE
14 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
GND
INPUTS
MIL-STD-1835 CDFP3-F14
A1
B1
Y1
A2
B2
Y2
MIL-STD-1835 CDIP2-T14
Quad 2-Input AND Gate
1
2
3
4
5
6
7
TRUTH TABLE
1
2
3
4
5
6
7
TOP VIEW
TOP VIEW
Radiation Hardened
Bn
H
H
L
L
Spec Number
14
13
12
11
10
9
8
File Number
14
13
12
11
10
9
8
VCC
B4
A4
Y4
B3
A3
Y3
OUTPUTS
(3, 6, 8, 11)
Yn
H
L
L
L
Yn
518842
2136.2
VCC
B4
A4
Y4
B3
A3
Y3

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HCTS08HMSR Summary of contents

Page 1

... C to +125 C Intersil Class S Equivalent o HCTS08D/ +25 C Sample Sample o HCTS08K/ +25 C Sample Sample o HCTS08HMSR +25 C Die CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | http://www.intersil.com or 407-727-9207 Copyright HCTS08MS Pinouts 2 /mg -9 Errors/Bit-Day 12 Rads (Si)/Sec +125 ...

Page 2

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage ...

Page 3

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Input to Output TPHL VCC = 4.5V TPLH VCC = 4.5V NOTES: 1. All voltages referenced to device GND measurements assume RL = 500 , CL = 50pF, Input TR ...

Page 4

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETERS SYMBOL Noise Immunity FN VCC = 4.5V, VIH = 2.25V, Functional Test VIL = 0.8V at 200K RAD, (Note 3) Input to Output TPHL VCC = 4.5V TPLH VCC = ...

Page 5

TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OPEN GROUND STATIC BURN-IN I TEST CONDITIONS (Note 10, 12, 13 STATIC BURN-IN II TEST CONNECTIONS (Note ...

Page 6

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 7

AC Timing Diagrams VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL FIGURE 1 AC VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 HCTS08MS AC Load Circuit TPHL ...

Page 8

Die Characteristics DIE DIMENSIONS mils 2.20 x 2.24mm METALLIZATION: Type: SiAl Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND ...

Page 9

Packaging -A- - bbb BASE S2 PLANE -C- SEATING PLANE aaa ccc NOTES: 1. Index ...

Page 10

Packaging (Continued) e PIN NO AREA - 0.004 0.036 - SEATING AND BASE PLANE c1 LEAD FINISH BASE (c) METAL b1 ...

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