ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 48

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ORT82G5-1BM680C

Manufacturer Part Number
ORT82G5-1BM680C
Description
0.6 to 3.7 Gbps XAUI and FC FPSCs
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
Lattice Semiconductor
Figure 29. Receive Clocking for a Dual Alignment in a Single Quad (Similar Connections Would Be Used for
Quad B)
For receive quad alignment, RSYS_CLK_[A1,B1] and RSYS_CLK_[A2,B2] can be tied together as shown for quad
A and B in Figure 30. In receive eight-channel alignment, either RCK78A or RCK78B can be used to source
RSYS_CLK_[A1,A2] and RSYS_CLK_[B1,B2] as shown in Figure 31.
Figure 30. Clocking for Quad Alignment in a Single Quad (Similar Connections Would Be Used for Quad B)
All Clocks at
78.125 MHZ
All Clocks at
78.125 MHZ
FPGA
Logic
FPGA
Logic
RSYS_CLK_A1
TSYS_CLK_AA
TSYS_CLK_AB
TSYS_CLK_AC
RSYS_CLK_A2
TSYS_CLK_AD
TSYS_CLK_AA
RSYS_CLK_A1
TSYS_CLK_AB
TSYS_CLK_AC
RSYS_CLK_A2
TSYS_CLK_AD
RWCKAD
RWCKAA
RWCKAB
RWCKAC
RCK78A
TCK78A
RWCKAA
RWCKAB
RWCKAC
RWCKAD
RCK78A
TCK78A
Common Logic, Quad A
Common Logic, Quad A
Channel AD
Channel AA
Channel AB
Channel AC
Channel AD
Channel AA
Channel AB
Channel AC
48
ORCA ORT42G5 and ORT82G5 Data Sheet
2
2
Two Bidirectional Channels
Two Bidirectional Channels
REFCLK[P:N]_A
156.25 MHz
Four Bidirectional Channels
REFCLK[P:N]_A
156.25 MHz
of 3.125 Gbps
of 3.125 Gbps
of 3.125 Gbps
Serial Data
Serial Data
Serial Data

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