ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 82

• Manufacturer Part Number: ORT82G5-1BM680C
• Description: 0.6 to 3.7 Gbps XAUI and FC FPSCs
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Table 40. Pin Descriptions (Continued)
MPI_CLK
MPI_TEA
MPI_RTRY
D[0:31]
DP[0:3]
DIN
DOUT
TESTCFG
(ORT82G5 only)
1. The FPGA States of Operation section in the ORCA Series 4 FPGAs data sheet (ORT82G5 only) contains more information on how to con-
trol these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the timing of the simulta-
neous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
Symbol
I/O
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.
I/O Selectable data bu
I/O After configuration, if MPI is not used, the pins are user-programmable I/O pins.
I/O Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15],
I/O After configuration, this pin is a user-programmable I/O pin.
I/O After configuration, DOUT is a user-programmable I/O pin.
I/O After configuration, TESTCFG is a user programmable I/O pin.
O A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on the
O This pin requests the MPC860 to relinquish the bus and retry the cycle.
O D[7:3] output internal status for asynchronous peripheral mode when RD is low.
O During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained
I
I
I
I
This is the PowerPC synchronous, positive-edge bus clock used for the
a source of the clock for the Embedded System Bus. If MPI is used this will be the AMBA bus
clock.
internal system bus for the current transaction.
transaction and driven by MPI in a read transaction.
D[7:0] receive configuration data during master parallel, peripheral, and slave parallel configu-
ration modes when WR is low and each pin has a pull-up enabled. During serial configuration
modes, D0 is the DIN input.
DP[2] for D[16:23], and DP[3] for D[24:31].
After configuration, if MPI is not used, the pins are user-programmable I/O pin.
During slave serial or master serial configuration modes, DIN accepts serial configuration data
synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. During con-
figuration, a pull-up is enabled.
slave devices. Data out on DOUT changes on the rising edge of CCLK.
During configuration this pin should be held high, to allow configuration to occur. A pull up is
enabled during configuration.
s
width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write
82
ORCA ORT42G5 and ORT82G5 Data Sheet
Description
1
1
1
MPI
interface. It can be
1
1
1
1
1