8S89834AKILF IDT [Integrated Device Technology], 8S89834AKILF Datasheet - Page 2

• Manufacturer Part Number: 8S89834AKILF
• Description: Low Skew, 2-to-4 LVCMOS/LVTTL-to-LVPECL/ECL Clock Multiplexer
• Manufacturer: IDT [Integrated Device Technology]

ICS8S89834I Data Sheet
Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
ICS8S89834AKI REVISION A FEBRUARY 4, 2010
Symbol
R
Number
PULLUP
15, 16
7, 14
1, 2
3, 4
5, 6
10
11
12
13
8
9
Parameter
Input Pullup Resistor
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q0, nQ0
Name
SEL
V
IN2
IN1
V
EN
nc
EE
cc
Unused
Output
Output
Output
Output
Power
Power
Input
Input
Input
Input
Type
Pullup
Pullup
Pullup
Pullup
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Positive supply pins.
Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ outputs will
go HIGH on the next LOW transition at IN inputs. Input threshold is V
37k
clocked on the falling edge of the input signal IN1, IN2.
LVTTL/LVCMOS interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
No connect.
Select clock input. When LOW, selects IN2 and when HIGH selects IN1.
LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Negative supply pin.
Differential output pair. LVPECL/ECL interface levels.
Test Conditions
Ω
pullup resistor. Default state is HIGH when left floating. The internal latch is
2
LOW SKEW, 2-TO-4 LVCMOS/LVTTL-TO-LVPECL/ECL CLOCK MULTIPLEXER
Minimum
©2010 Integrated Device Technology, Inc.
Typical
37
Maximum
CC
/2V. Includes a
Units
k
Ω