HCTS299DMSR INTERSIL [Intersil Corporation], HCTS299DMSR Datasheet
HCTS299DMSR
Related parts for HCTS299DMSR
HCTS299DMSR Summary of contents
Page 1
... The HCTS299MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family with TTL input compatibility. Ordering Information PART NUMBER TEMPERATURE RANGE HCTS299DMSR HCTS299KMSR HCTS299D/Sample HCTS299K/Sample HCTS299HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | http://www ...
Page 2
Functional Block Diagram STANDARD OUTPUT S1 DS7 VCC OE1 OE2 HCTS299MS BUS LINE OUTPUTS I/O7 I/O5 I/ ...
Page 3
FUNCTION MR CP Reset (Clear Shift Right H H Shift Left H H Hold (Do Nothing) H Parallel Load H H FUNCTION OE1 Read Register Load Register X Disable I ...
Page 4
Absolute Maximum Ratings Supply Voltage (VCC -0.5 to +7.0V Input Voltage Range, All Inputs . ...
Page 5
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CLK to I/On TPHL, VCC = 4.5V TPLH CLK to Q0, Q7 TPHL, VCC = 4.5V TPLH MR to Output TPHL VCC = 4.5V OEn to Output TPZH VCC = 4.5V TPHZ ...
Page 6
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL Setup Time S1, S0 TSU VCC = 4.5V to CLK Hold Time DS0, TH VCC = 4.5V DS7, I/On, S0 CLK Recovery Time MR TREC VCC = 4.5V to CLK ...
Page 7
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL MR to Output TPHL VCC = 4.5V OEn to Output TPZH VCC = 4.5V TPHZ TPZL VCC = 4.5V TPLZ NOTES: 1. All voltages referenced to device GND ...
Page 8
CONFORMANCE GROUPS METHOD Group E Subgroup 2 5005 NOTE: 1. Except FN test which will be performed 100% Go/No-Go. OPEN GROUND STATIC BURN-IN I TEST CONNECTIONS (Note 16, 18, 19 STATIC BURN-IN ...
Page 9
Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...
Page 10
AC Timing Diagrams and Load Circuit INPUT LEVEL TPHL VS I/On FIGURE 1. CLOCK PRE-REQUISITE AND PROPAGATION DELAYS INPUT LEVEL VS VS DS0, DS7 OR I/On TH(L) TSU( FIGURE 3. DATA ...
Page 11
Three-State Low Timing Diagrams VIH INPUT VS VIL TPZL VOZ VT OUTPUT VOL Three-State LOW VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VT 1.30 VW 0.90 VIL 0 GND 0 Three-State High Timing Diagrams VIH INPUT VS ...
Page 12
Die Characteristics DIE DIMENSIONS: 123 x 94 mils METALLIZATION: Type: SiAl Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: 100 ...
Page 13
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, ...