HCTS74K INTERSIL [Intersil Corporation], HCTS74K Datasheet

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HCTS74K

Manufacturer Part Number
HCTS74K
Description
Radiation Hardened Dual-D Flip-Flop with Set and Reset
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS74MS is a Radiation Hardened positive
edge triggered flip-flop with set and reset.
The HCTS74MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS74MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS74DMSR
HCTS74KMSR
HCTS74D/Sample
HCTS74K/Sample
HCTS74HMSR
Bit-Day (Typ)
- VIL = 0.8V Max
- VIH = VCC/2 Min
PART NUMBER
10
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
TEMPERATURE RANGE
12
o
C to +125
RAD (Si)/s
-55
-55
o
o
C to +125
C to +125
+25
+25
+25
o
o
o
o
C
C
C
C
2
/mg
-9
o
o
C
C
Errors/
460
Pinouts
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
GND
SCREENING LEVEL
CP1
R1
D1
Q1
Q1
S1
HCTS74MS
MIL-STD-183S CDFP3-F14, LEAD FINISH C
MIL-STD-183S CDIP2-T14, LEAD FINISH C
FLATPACK PACKAGE (FLATPACK)
14 LEAD CERAMIC DUAL-IN-LINE
14 LEAD CERAMIC METAL SEAL
METAL SEAL PACKAGE (SBDIP)
Flip-Flop with Set and Reset
GND
CP1
Radiation Hardened Dual-D
R1
D1
Q1
Q1
S1
1
2
3
4
5
6
7
1
2
3
4
5
6
7
TOP VIEW
TOP VIEW
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
14
13
12
11
10
9
8
14
13
12
10
11
Spec Number
9
8
File Number
PACKAGE
VCC
R2
D2
CP2
S2
Q2
Q2
VCC
R2
D2
CP2
S2
Q2
Q2
518626
2143.2

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HCTS74K Summary of contents

Page 1

... SBDIP Package (D suffix). Ordering Information PART NUMBER TEMPERATURE RANGE HCTS74DMSR HCTS74KMSR HCTS74D/Sample HCTS74K/Sample HCTS74HMSR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HCTS74MS Pinouts MIL-STD-183S CDIP2-T14, LEAD FINISH C ...

Page 2

Functional Diagram S 4(10) D 2(12) R 1(13) CP 3(11) SET NOTE Logic Level Low Logic Level High Don’t Care = Transition from Low to High Level Q0 ...

Page 3

Absolute Maximum Ratings Supply Voltage (VCC -0.5V to +7.0V Input Voltage Range, All Inputs . . ...

Page 4

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL TPHL VCC = 4.5V TPLH VCC = 4. TPLH VCC = 4. TPHL VCC = 4. TPHL VCC = ...

Page 5

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETERS SYMBOL Quiescent Current ICC VCC = 5.5V, VIN = VCC or GND Output Current (Sink) IOL VCC = 4.5V, VIN = VCC or GND, VOUT = 0.4V Output Current IOH VCC ...

Page 6

CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B Subgroup B-5 Subgroup B-6 Group D NOTES: 1. Alternate Group A testing in ...

Page 7

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 8

AC Timing Diagrams and Load Circuit VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL Pulse Width, Setup, Hold Timing Diagram Positive Edge Trigger INPUT TW VIH VS VIL TH TSU TW INPUT CP ...

Page 9

Die Characteristics DIE DIMENSIONS mils 2.25 x 2.24mm METALLIZATION: Type: SiAl Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND ...

Page 10

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, ...

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