HS-3000 BOSER [BOSER Technology Co., Ltd], HS-3000 Datasheet - Page 17
HS-3000
Manufacturer Part Number
HS-3000
Description
386 ISA Bus SBC
Manufacturer
BOSER [BOSER Technology Co., Ltd]
Datasheet
1.HS-3000.pdf
(46 pages)
- Current page: 17 of 46
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Period PINS 1-2 PINS 3-4 PINS 5-6 PINS 7-8
(default)
110 sec
220 sec
10 sec
20 sec
1 sec
2 sec
The watchdog timer is disabled after the system power-on. The
watchdog timer can be enabled by a Enable cycle with reading the
control port (443H), a Refresh cycle with reading the control port
(443H) and a Disable cycle by reading the watchdog timer disable
control port (043H). After a Enable cycle of WDT, user must constantly
proceed a Refresh cycle to WDT before its period setting comes ending
of every 1, 2, 10, 20, 110 or 220 seconds (Please reference to the
selection table of JP14 for WDT Time Out period setting). If the Refresh
cycle does not active before WDT period cycle, the onboard WDT
architecture will issue a Reset or NMI cycle to the system. The
watchdog timer controlled by two I/O ports.
The following sample program shows how to Enable, Disable and
Refresh the watchdog timer:
WDT_EN_RF
WDT_DIS
WT_Enable
JP9: Watchdog Timer Active Type Select
JP14: Watchdog Timer Out Period Select
Open
Open
Open
Open
Short
Short
Short 1-2 (default)
PUSH
MOV
IN
POP
POP
RET
443H
043H
Short 2-3
Open
JP9
Open
Open
Open
Open
Short
Short
EQU
EQU
PUSH
DX
DX,WDT_EN_RF
AL,DX
DX
AX
I/O Read
I/O Read
0433H
0043H
AX
Description
System Reset
Short
Short
Open
Open
Open
Open
Active NMI
Disabled
; enable the WDT
; get back AX, DX
Enable/Refresh cycle
Disable cycle
Open
Short
Open
Short
Open
Short
; keep AX DX
1
3
2
1
11
8
7
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