AAT4292IJQ-T1 ANALOGICTECH [Advanced Analogic Technologies], AAT4292IJQ-T1 Datasheet - Page 11

• Manufacturer Part Number: AAT4292IJQ-T1
• Description: Seven Channel High-Side I/O Expanderimage
• Manufacturer: ANALOGICTECH [Advanced Analogic Technologies]

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Application Information
Thermal Considerations
The AAT4292 is designed to deliver continuous output
load currents. Due to its high integration, care must be
taken in designing for higher load conditions. If greater
loads are required, outputs can be tied together to
deliver higher power to a given load.
For the thermal calculation, assuming that the total cur-
rent capability of the seven channels is I
nel has the same current which is
Where:
P
P
R
For example, at 25
bility is P
The current capability for each channel is I
At 85
= 440 - (85 - 25)4.4 = 176mW, then I
= 5.0V. The current capability for each channel is I
121mA.
Output Sequencing
If output sequencing is not necessary, then a pulse burst
of 33 address clocks followed by 1 data clock will switch
on all of the outputs simultaneously. Alternately, the
OUT3 to OUT7 will be switched on simultaneously on the
first rising edge of the EN/SET pin after the t
4292.2008.08.1.0
P
D
DERATE
TOTAL
DS(ON)
= 440mW when T
o
= 7I
C ambient, the AAT4292 power capability is P
= 4.4mW/°C
= 1.7Ω (maximum) when V
TOTAL
OUT
2
R
= 440mW, then I
DS(ON)
TM
o
= 7
C ambient, the AAT4292 power capa-
A
= 25°C
I
TOTAL
7
2
R
TOTAL
DS(ON)
≅ 1.35A at V
IN
I
OUT
= P
= 5.0V
=
TOTAL
I
TOTAL
D
TOTAL
7
- P
, then
≅ 0.85A at V
OUT
DERATE
, each chan-
LAT
= 192mA.
w w w . a n a l o g i c t e c h . c o m
IN
timeout.
(T
= 5.0V.
A
OUT
- 25)
TOTAL
=
IN
Output sequencing is accomplished via a series of pulses
on the EN/SET pin. Each time a new pulse burst is
asserted on EN/SET, the AAT4292 internal clock counter
starts to count and sends the counted clock number to
the register. After the t
counter is reset and waits for the next pulse burst. For
example, to sequence the outputs in order from OUT1 to
OUT7, seven clock bursts are input on the EN/SET pin.
From Table 1 and Table 2, the first bust of 34 address
clocks followed by 32 data clocks turns on OUT1. The
next burst of 33 address clocks followed by 32 data
clocks will add OUT2. Then the burst of 33 address
clocks followed by 16 data clocks will add OUT3; the
burst of 33 address clocks followed by 8 data clocks will
add OUT4; the burst of 33 address clocks followed by 4
data clocks will add OUT5; the burst of 33 address clocks
followed by 2 data clocks will add OUT6; the burst of 33
address clocks followed by 1 data clock will add OUT7.
Likewise, the outputs can be turned on/off in any order
by adding the corresponding clock bursts.
Input Capacitor
Normally, the input capacitor value could be ten times
that of the total load capacitors. If the device outputs
OUT1 to OUT7 have capacitor loads, depending on the
load capacitor value, it is recommended that a 1μF to
10μF 0603 or 0805 ceramic capacitor be placed as close
as possible between VIN and GND. For example, if the
capacitor load at each output is 0.1μF, the Murata
GRM21BR61C106K ceramic capacitor (10μF/16V/0805/
X5R) or a similar capacitor could be used. This helps to
provide a low impendence loop to charge the load capac-
itors during the MOSFET switches' turn-on transient and
keep the V
Seven Channel High-Side I/O Expander
IN
voltage stable.
PRODUCT DATASHEET
LAT
timeout, the internal clock
AAT4292
11