AAT4292IJQ-T1 ANALOGICTECH [Advanced Analogic Technologies], AAT4292IJQ-T1 Datasheet - Page 9

• Manufacturer Part Number: AAT4292IJQ-T1
• Description: Seven Channel High-Side I/O Expanderimage
• Manufacturer: ANALOGICTECH [Advanced Analogic Technologies]

age. When the device is switched ON, the gate voltage
is quickly increased to the threshold level of the MOSFET.
Once at this level, the current begins to slew as the gate
voltage is slowly increased until the MOSFET becomes
fully enhanced. Once it has reached this point, the gate
is quickly increased to the full input voltage and R
minimized.
The ON/OFF states of the seven MOSFET switches are
controlled by the EN/SET serial clock input. An internal
control counter is clocked on the rising edges of the EN/
SET pin and is decoded into 128 possible states of the
MOSFET (see Table 1 and Table 2). The counter can be
clocked at speeds up to 1MHz, but the count value is not
latched until clocking has stopped and the EN/SET pin
has remained high for the t
1.15μs typical). The first rising edge of EN/SET enables
the AAT4292 and is counted as the first clock.
There are four address switch bank in AAT4292, which is
selected by the corresponding rising edges 33 to 36,
after remaining the EN/SET high for the t
then the clock number is latched and the relevant
address switch bank (0 to 3) is asserted. Next, the cor-
responding rising edges of Data from 1 to 32 can be
serial submitted, and closed by the EN/SET remaining
high for t
status is updated accordingly.
The AAT4292 is disabled after the EN/SET pin has tran-
sitioned and remained in a logic low for t
the quiescent current drops to 0.1μA typically.
SmartSwitch
4292.2008.08.1.0
LAT
timeout. After the timeout t
TM
LAT
timeout (approximate
OFF
LAT
, the outputs
timeout, and
LAT
w w w . a n a l o g i c t e c h . c o m
timeout,
DS(ON)
is
AS
The ON/OFF states of the seven output channels are con-
trolled by the EN/SET serial data input. An internal con-
trol counter is clocked on the rising edge of the EN/SET
pin and is decoded into one of 128 possible states using
a short address and data word (see Tables 1 and 2).
AS
SET pin to address and load the registers, as illustrated
in Figure 1. AS
address (33 to 36 edges) after the EN/SET pin has been
held high for time t
of the EN/SET pin and decodes them into one of four
addresses corresponding to the address table (Table 1),
or 1 of 32 data settings corresponding to the switch code
table (Table 2). The combined address and data is used
to decode one of 128 possible switch states. Address and
Data are differentiated by the number of rising edges on
the EN/SET pin. 1 to 32 rising edges signifies Data, and
33 to 36 rising edges signifies Address. The counter can
be clocked at speeds up to 1MHz, such that intermediate
states are not visible. The first rising edge of EN/SET
enables the IC and turns the switches OUT3-OUT7 on.
Once the final clock cycle is received, the EN/SET pin is
held high to maintain the device setting. The device is
disabled after the EN/SET pin transitions to a logic low
state for t
Address Code
2
Seven Channel High-Side I/O Expander
Cwire relies on the number of rising edges of the EN/
2
Cwire Serial Interface
Address Switch
Bank Code
Table 1: AS
OFF
0
1
2
3
timeout (approximate 1.3μs typical).
2
Cwire latches data (1 to 32 edges) or
LAT
PRODUCT DATASHEET
. The interface records rising edges
2
Cwire Address Table.
AAT4292
Rising Edges
EN/SET
33
34
35
36
9