ASC7512 ETC2 [List of Unclassifed Manufacturers], ASC7512 Datasheet - Page 10

• Manufacturer Part Number: ASC7512
• Description: DIGITAL TEMPERATURE SENSOR WITH INTEGRATED FAN CONTROL
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Operation
The aSC7512 has an emergency alarm function,
limits and will also respond to a remote diode open circuit
failure. These limits are settable separately for Zone 1
and Zone 2 sensors. Any alarm condition is reported
individually in the status register and may be read at any
time on the SMBus. Alarm conditions are logically
combined and used to drive an open-drain output, the
This output pin may be used as an interrupt signal the
CPU or to turn on remote drivers for fans or indicators.
The ALERT pin will remain asserted until it has been
reset by the host via the SMBus.
Figure 7 shows use of the ALERT high and low limits.
The user sets up the alarm by writing the upper and lower
limit temperatures into the limit registers over the SMBus.
After each measurement, the comparator tests the
readings against the programmed limits and if the
measurement exceeds the high limit is or is equal to or
less-than the low limit, it will assert the particular alarm
bits in the status register and cause the ALERT pin to go
low.
The status bits will remain high until the status register is
read and then, if the condition is no longer present those
bits will be reset, otherwise they will remain high until the
conditions are no longer met and the register is read
again. The same sequence applies to the local readings
and limits.
© Andigilog, Inc. 2006
ALERT
ALERT that is optionally assigned to pin 6, the TACH /
ALERT pin. ALERT is determined by both high and low
ALERT output, (pin 6).
ALERT
ZN1 High ALERT Limit
ZN1 Low ALERT Limit
Status Register Read
Status Bit-4, RHIGH
Status Bit-3, RLOW
Figure 7
ARA Response
Limits
Output
ALERT Pin 6
Temperature
Conversion
ALERT
Limits and Responses
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The ALERT pin will remain low until the status bits have
been reset and an Alert Response has been issued by
the master and responded by the aSC7512. This flow is
described below.
The user may mask-out or disable the ALERT signal pin
should it be necessary to prevent a processor interrupt.
This is controlled by setting bit 7 of the configuration
register.
SMBus Alert Output
The ALERT pin may be used to signal an SMBus Alert to
the host processor. This is a special mode of the SMBus
interface that requires the SMBus host to send an Alert
Response Address (ARA) to all slaves sharing the
alerting device. This sequence is described below and in
Figure 6.
The sequence of servicing this interrupt is as follows:
ALERT pin in order to isolate clear and service the
1.
2.
3.
4.
5.
6 low.
The SMBus master begins a read operation with
a start followed by the ARA response address,
0001 100. This is an SMBus General Call
Address to be used only for requesting an alert
response.
The device providing the ALERT signal responds
to this by providing an ACK followed by its own
bus address, an aSC7512 will provide, 101
1000, with the LSB of the data byte set to 1. A
NACK response is expected from all devices not
giving an ALERT .
If more than one device responds, the device
with the lowest device address will have priority
and will be serviced first by the master.
The service routine must read the status register
of the alerting device to determine the nature of
the alert. If the alerting condition is still present,
the status bit will remain set, continuing to
activate the ALERT pin. If the condition is
removed, the status bit will be cleared and an
additional
ALERT is asserted by the aSC7512 driving pin
ALERT pin.
ARA
will
August 2006 - 70A05003
now
aSC7512
de-assert
the