ASC7512 ETC2 [List of Unclassifed Manufacturers], ASC7512 Datasheet - Page 8

• Manufacturer Part Number: ASC7512
• Description: DIGITAL TEMPERATURE SENSOR WITH INTEGRATED FAN CONTROL
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

set, the master must perform a repeat start condition that
indicates to the aSC7512 that a read is about to occur. It is
important to note that if the repeat start condition does not
occur, the aSC7512 will assume that a write is taking place,
and the selected register will be overwritten by the
upcoming data on the data bus. The read sequence is
described in Figure 4. After the start condition, the master
must again send the device address and read/write bit.
This time the R/ W bit must be set to 1 to indicate a read.
The rest of the read cycle is the same as described in the
previous paragraph for reading from a preset pointer
location.
If the pointer is already pointing to the desired register, the
master can read from that register by setting the R/ W bit
(following the slave address) to a 1. After sending an ACK,
© Andigilog, Inc. 2006
SDA
SDA
SCL
SCL
without stop by Master
Start
Start
S
S
Register Address
SMBus Device Address Byte (58h)
SMBus Device Address Byte (58h)
1
Pointer Set
1
1
1
(Figure 2.)
0
0
1
1
1
1
0
0
+
0
0
Re-start
0
0
S
SMBus Device Address Byte (58h)
R/W
R/W
1
Figure 2 Register Address Pointer Set
1
aSC7512
aSC7512
9
9
ACK
from
ACK
from
A
A
0
A7
A7
1
1
1
Figure 3 Register Write
Figure 4 Register Read
A6
A6
Register Address Byte
Register Address Byte
1
A5
A5
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0
A4
A4
0
A3
A3
- 8 -
0
A2
A2
the aSC7512 will begin transmitting data during the
following clock cycle. After receiving the 8 data bits, the
master device should respond with a NACK followed by a
stop condition.
If the master is reset while the aSC7512 is in the process of
being read, the master should perform an SMBus reset.
This is done by holding the data or clock low for more than
35ms, allowing all SMBus devices to be reset. This follows
the SMBus 2.0 specification of 25-35ms.
When the aSC7512 detects an SMBus reset, it will prepare
to accept a new start sequence and resume
communication from a known state.
R/W
aSC7512
A1
A1
ACK
from
9
A
aSC7512
A0
A0
D7
1
aSC7512
ACK
from
9
9
ACK
from
A
A
D6
Stop
By
Master
D7
Register Data Byte
1
D5
D6
Register Data Byte
D4
D5
D3
D4
D2
D3
D1
D2
August 2006 - 70A05003
D0
Master
NACK
D1
from
9
N
aSC7512
aSC7512
D0
Stop
by
Master
ACK
from
9
A
Stop
by
Master