DMA2275 MICRONAS [Micronas], DMA2275 Datasheet - Page 18

• Manufacturer Part Number: DMA2275
• Description: DMA 2275, DMA 2286 C/D/D2-MAC Descrambler
• Manufacturer: MICRONAS [Micronas]

DMA 2275, DMA 2286
Table 8–3, continued
8.3. DRAM Interface
The data transfer between descrambler chip and acqui-
sition DRAM interface controlled by the FP. The external
64 k x 1 bit DRAM has to store the following data
streams:
– line 625
– packet bus
– IM bus
The 1 bit DRAM interface offers a maximum data rate of
5.0625 Mbit/s by using four 20.25 MHz cycles for one
page mode read or write access. A 150 ns DRAM fulfills
the access time requirements. Fig. 9–14 shows the
DRAM interface waveform. Refresh of the DRAM is con-
trolled by the FP, which starts a number of refresh cycles
within every line. An 8 bit refresh is performed to allow
the use of 256 Kbit DRAMs.
The acquisition DRAM is used on one side to store re-
ceived packet data and line 625 information needed by
the CCU and the conditional access subsystem (CASS)
and on the other side to store control information needed
by the descrambler chip (e.g. control words, filter coeffi-
cients, packet addresses etc.). Therefore, the descram-
bler chip does not include special IM bus registers ex-
cept those for subaddressing and sound processing (on
the DMA 2286 only).
The upper end of the DRAM address space can be used
as a scratch buffer for the CCU software. This DRAM
area is also refreshed and will never be used by the des-
crambler chip.
18
Address
209
210
Label
PSL
PSH
PDL
PDH
28 byte/40ms
2 x 96 byte/448 s
Bit No.
0–7
8–15
0–7
8–15
3430000 bit/s
Function
packet 0 syndrom low byte
packet 0 syndrom high byte
PSL + PSH = 0:
PSL + PSH > 0:
packet 0 data low byte
packet 0 data high byte
500000 bit/s
5600 bit/s
packet 0 received without error
packet 0 received with error