LH5P860D-80 SHARP [Sharp Electrionic Components], LH5P860D-80 Datasheet

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LH5P860D-80

Manufacturer Part Number
LH5P860D-80
Description
CMOS 512K (64K x 8) Pseudo-Static RAM
Manufacturer
SHARP [Sharp Electrionic Components]
Datasheet
1.LH5P860D-80.pdf (13 pages)
LH5P860
FEATURES
65,536
Access time: 80 ns (MAX.)
Cycle time: 140 ns (MIN.)
Single +5 V power supply
Pin compatible with 1M standard SRAM
Power consumption (MAX.):
TTL compatible I/O
512 refresh cycles/8 ms (MAX.)
Available for auto-refresh and self-refresh
modes
Packages:
Operating: 440 mW
Self refresh (TTL level): 5.5 mW
Self refresh (CMOS level): 2.75 mW
32-pin, 600-mil DIP
32-pin, 525-mil SOP
8 bit organization
CMOS 512K (64K
DESCRIPTION
ganized as 65,536
con-gate CMOS process technology. With its built-in
oscillator, it is easy to refresh memories without an
external clock.
PIN CONNECTIONS
The LH5P860 is a 512K-bit Pseudo-Static RAM or-
32-PIN DIP
32-PIN SOP
Figure 1. Pin Connections for DIP and
RFSH
GND
I/O
I/O
I/O
A
A
NC
A
A
A
A
A
A
A
A
14
12
7
6
5
4
3
2
1
0
0
1
2
SOP Packages
10
13
14
15
16
8 bits. It is fabricated using sili-
12
11
2
3
4
5
6
7
8
9
1
8) Pseudo-Static RAM
32
30
29
28
27
26
25
24
23
22
20
19
18
17
31
21
V
A
CE
R/W
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
15
13
8
9
11
10
2
1
7
6
5
4
3
TOP VIEW
5P860-1
1

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LH5P860D-80 Summary of contents

Page 1

LH5P860 FEATURES 65,536 8 bit organization Access time (MAX.) Cycle time: 140 ns (MIN.) Single +5 V power supply Pin compatible with 1M standard SRAM Power consumption (MAX.): Operating: 440 mW Self refresh (TTL level): 5.5 mW Self ...

Page 2

LH5P860 COLUMN ADDRESS BUFFER ROW ...

Page 3

CMOS 512K (64K 8) Pseudo-Static RAM ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Applied voltage on all pins Output short circuit current Power dissipation Operating temperature Storage temperature NOTE: 1. The maximum applicable voltage on any pin with respect to GND. RECOMMENDED ...

Page 4

LH5P860 CHARACTERISTICS PARAMETER Random read, write cycle time Read modify write cycle time CE pulse width CE precharge time Address setup time Address hold time Read command setup time Read command hold time CE access time ...

Page 5

CMOS 512K (64K 8) Pseudo-Static RAM R I/O ...

Page 6

LH5P860 R I ...

Page 7

CMOS 512K (64K 8) Pseudo-Static RAM R ...

Page 8

LH5P860 R I/O - ...

Page 9

CMOS 512K (64K 8) Pseudo-Static RAM R ...

Page 10

LH5P860 R I ...

Page 11

CMOS 512K (64K 8) Pseudo-Static RAM RFSH I/O - ...

Page 12

LH5P860 PACKAGE DIAGRAMS 32DIP (DIP032-P-0600 41.30 [1.626] 40.70 [1.602] 2.54 [0.100] 0.60 [0.024] TYP. 0.40 [0.016] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 32SOP (SOP032-P-0525) 0.50 [0.020] 0.30 [0.012 20.80 [0.819] 20.40 [0.803] MAXIMUM LIMIT ...

Page 13

CMOS 512K (64K 8) Pseudo-Static RAM ORDERING INFORMATION LH5P860 Device Type Package Example: LH5P860N-80 (CMOS 512K (64K x 8) Pseudo-Static RAM, 80 ns, 32-pin, 525-mil SOP Speed 80 Access Time (ns) D 32-pin, 600-mil DIP (DIP032-P-0600) N ...

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