K7N161801M SAMSUNG [Samsung semiconductor], K7N161801M Datasheet - Page 12

• Manufacturer Part Number: K7N161801M
• Description: 512Kx36 & 1Mx18-Bit Pipelined NtRAM TM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K7N163601M
K7N161801M
Dout
AC TIMING CHARACTERISTICS
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled
Cycle Time
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High (WE, BW
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
CKE Hold from Clock High
Data Hold from Clock High
Write Hold from Clock High (WE, BW
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
ZZ Low to Power Up
2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low, A Read cycle is defined by WE High with ADV Low,
4. To avoid bus contention, At a given voltage and temperature t
low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
(0 C,3.465V) than t
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
Both cases must meet setup and hold times.
The specs as shown do not imply bus contention because t
Output Load(A)
PARAMETER
Zo=50
HZC
, which is a Max. parameter(worst case at 70 C,3.135V)
X
)
X
)
RL=50
30pF*
* Including Scope and Jig Capacitance
(V
DD
SYMBOL
t
t
t
t
=3.3V+0.165V/-0.165V, T
t
HZOE
t
t
ADVS
t
t
ADVH
t
t
t
t
LZOE
t
t
CYC
t
t
t
HZC
t
t
t
CES
t
CSS
t
CEH
t
CSH
PDS
PUS
LZC
WH
OH
WS
CD
OE
CH
CL
AS
DS
AH
DH
VL=1.5V for 3.3V I/O
V
DDQ
512Kx36 & 1Mx18 Pipelined NtRAM
MIN
Fig. 1
6.0
1.5
1.5
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
LZC
LZC
0
2
2
- 12 -
-
-
-
-
/2 for 2.5V I/O
is more than t
-16
is a Min. parameter that is worst case at totally different test conditions
MAX
3.5
3.5
3.0
3.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MIN
HZC.
6.7
1.5
1.5
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0
2
2
-
-
-
-
A
=0 to 70 C)
-15
353
MAX
Output Load(B),
(for t
3.8
3.8
3.0
3.0
Dout
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LZC
1538
MIN
, t
7.5
1.5
1.5
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0
2
2
-
-
-
-
LZOE
-13
, t
MAX
HZOE
4.2
4.2
3.5
3.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
& t
MIN
10.0
1.5
1.5
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
HZC
0
2
2
-
-
-
-
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319
5pF*
)
-10
December 1999
MAX
5.0
5.0
3.5
3.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1667
Rev 1.0
UNIT
cycle
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TM