T5743P3 ATMEL [ATMEL Corporation], T5743P3 Datasheet - Page 10

• Manufacturer Part Number: T5743P3
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

Polling Mode
10
T5743
Figure 9. Generation of the Basic Clock Cycle
Pin MODE can now be set in accordance with the desired clock cycle T
the following application relevant parameters:
•
•
•
•
•
Most applications are dominated by two transmission frequencies: f
mainly used in USA, f
dependent parameters on this electrical characteristics display three conditions for each
parameter.
•
•
•
The clock cycle of some function blocks depends on the selected baud-rate range
(BR_Range) which is defined in the OPMODE register. This clock cycle T
by the following formulas for further reference:
BR_Range = BR_Range0:
According to Figure 10, the receiver stays in polling mode in a continuous cycle of three
different modes. In sleep mode the signal processing circuitry is disabled for the time
period T
all signal processing circuits are enabled and settled. In the following bit-check mode,
the incoming data stream is analyzed bit by bit contra a valid transmitter signal. If no
valid signal is present, the receiver is set back to sleep mode after the period T
This period varies check by check as it is a statistical process. An average value for
T
consumption is I
The average current consumption in polling mode is dependent on the duty cycle of the
active mode and can be calculated as:
Bit-check
Timing of the polling circuit including bit check
Timing of the analog and digital signal processing
Timing of the register programming
Frequency of the reset marker
IF filter center frequency (f
Application USA (f
Application Europe (f
Other applications (T
The electrical characteristic is given as a function of T
Sleep
is given in the electrical characteristics. During T
while consuming low current of I
BR_Range1:
BR_Range2:
BR_Range3:
S
= I
Son
Send
XTO
. The condition of the receiver is indicated on Pin IC_ACTIVE.
XTO
Clk
= 433.92 MHz in Europe. In order to ease the usage of all T
= 4.90625 MHz, MODE = L, T
is dependent on f
= 6.76438 MHz, MODE = H, T
:14/:10
Divider
XTO
IF0
T
T
T
T
XClk
XClk
XClk
XClk
)
T
f
Clk
XTO
= 8 ´ T
= 4 ´ T
= 2 ´ T
= 1 ´ T
16
15
Clk
Clk
Clk
Clk
14
MODE
DVCC
XTO
XTO
S
= I
and on the logical state of Pin MODE.
Soff
L : USA(:10)
H: Europe(:14)
. During the start-up period, T
Clk
Startup
Clk
= 2.0383 µs)
Clk
).
= 2.0697 µs)
and T
Send
Bit-check
Clk
XClk
= 315 MHz is
4569A–RKE–12/02
. T
the current
Clk
is defined
controls
Bit-check
Startup
Clk
-
,
.