T5743P3 ATMEL [ATMEL Corporation], T5743P3 Datasheet - Page 14

• Manufacturer Part Number: T5743P3
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 13. Timing Diagram During Bit Check
Figure 14. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
14
( Lim_min = 14, Lim_max = 24 )
IC_ACTIVE
Bit check
Dem_out
Bit-check-
counter
( Lim_min = 14, Lim_max = 24 )
IC_ACTIVE
Bit check
Dem_out
Bit-check-
counter
T5743
Start-up mode
Start-up mode
T
T
Start-up
Start-up
0
0
T
T
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using above formulas, Lim_min and Lim_max can be determined according to the
required T
T
to the section ‘Receiving Mode’. The lower limit should be set to Lim_min ³ 10. The
maximum value of the upper limit is Lim_max = 63.
If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits
(N
Figure 13, Figure 14 and Figure 15 illustrate the bit check for the bit-check limits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits
are enabled during T
fined during that period. When the bit check becomes active, the bit-check counter is
clocked with the cycle T
Figure 13 shows how the bit check proceeds if the bit-check counter value CV_Lim is
within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
Figure 14 the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit
check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 15.
1
1
Lim_min
Lim_max
XClk
Bit-check
2 3 4 5 6
2 3 4 5 6
. The minimum edge-to-edge time t
= Lim_min ´ T
= (Lim_max –1) ´ T
) to prevent switching to receiving mode due to noise.
Lim_min
T
1
7 8 1
XClk
Bit-check mode
2
3
T
Bit-check
, T
2
4 5
3
Lim_max
1/2 Bit
4 5
6 7 8 9
Startup
XClk
6 7 8 9
XClk
Bit check failed ( CV_Lim < Lim_min )
. The output of the ASK/FSK demodulator (Dem_out) is unde-
and T
1/2 Bit
10
.
XClk
11 12
10
Bit-check mode
XClk
11 12 13 14
T
Bit-check
. The time resolution defining T
15 16 17 18 1 2 3 4 5 6
ee
Bit check ok
(t
Sleep mode
0
DATA_L_min
T
Sleep
, t
DATA_H_min
1/2 Bit
7 8 9 10 11 12 13 14 15 1 2 3 4
) is defined according
Lim_min
Bit check ok
and T
1/2 Bit
4569A–RKE–12/02
Lim_max
is