K7R321884M-FC16 SAMSUNG [Samsung semiconductor], K7R321884M-FC16 Datasheet - Page 3

• Manufacturer Part Number: K7R321884M-FC16
• Description: 1Mx36 & 2Mx18 QDRTM II b4 SRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K7R321884M
K7R323684M
PIN CONFIGURATIONS
Notes : 1. * Checked No Connect(NC) or Vss pins are reserved for higher density address, i.e. 3A for 72Mb, 10A for 144Mb and 2A fo r 288Mb.
PIN NAME
Notes: 1. C, C, K or K cannot be set to V
B W
G
M
A
B
C
D
E
F
H
K
L
N
P
R
J
0
, BW
2. When ZQ pin is directly connected to V
3. Not connected to chip pad internally.
SYMBOL
CQ, CQ
2. BW
D0-35
Q0-35
V
V
C, C
TMS
TCK
TDO
K, K
Doff
V
V
TDI
NC
SA
Z Q
1,
W
DDQ
R
REF
DD
SS
BW
TDO
Q27
Q29
Q30
Q32
Q33
Q35
D27
D28
D30
Doff
D31
D33
D34
0
C Q
1
controls write to D0:D8, BW
2
, B W
3
V
SS
V
Q18
Q28
Q21
Q31
Q24
Q34
TCK
D20
D29
D22
D32
D26
D35
REF
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M,
2
/SA*
10P,11N,11M,10K,11J,11G,10E,11D,11C,10N,9M,9L
9J,10G,9F,10D,9C,9B,3B,3C,2D,3F,2G,3J,3L,3M,2N
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
11P,10M,11L,11K,10J,11F,11E,10C,11B,9P,9N,10L
9A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
9K,9G,10F,9E,9D,10B,2B,3D,3E,2F,3G,3K,2L,3N
NC/SA*
V
(TOP VIEW)
Q19
Q20
Q22
Q23
Q25
Q26
D18
D19
D21
D23
D24
D25
SA
DDQ
REF
3
3P,1B,2C,1E,1F,2J,1K,1L,2M,1P
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
1C,1D,2E,1G,1J,2K,1M,1N,2P
1
voltage.
controls write to D9:D17, BW
DD
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
PIN NUMBERS
V
V
V
V
V
V
V
V
V
V
V
7B,7A,5A,5B
SA
SA
SA
W
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
4
SS
SS
SS
SS
8M,4N,8N
11A, 1A
2H,10H
6B, 6A
6P, 6R
3A,6C
11H
10R
11R
1H
2R
1R
K7R323684M(1Mx36)
4A
8A
BW
BW
V
V
V
V
V
V
V
V
V
SA
SA
SA
SA
5
SS
SS
DD
DD
DD
DD
DD
SS
SS
2
3
- 3 -
2
controls write to D18:D26 and BW
1Mx36 & 2Mx18 QDR
V
V
V
V
V
V
V
V
V
NC
SA
C
C
6
K
K
SS
SS
SS
SS
SS
SS
SS
SS
SS
BW
BW
V
V
V
V
V
V
V
V
V
SA
SA
SA
SA
7
SS
SS
DD
DD
DD
DD
DD
SS
SS
1
0
Block Write Control Pin,active when low
Output Driver Impedance Control Input
Output Power Supply ( 1.5V or 1.8V )
Write Control Pin,active when low
Read Control Pin,active when low
V
V
V
V
V
V
V
Input Clock for Output Data
V
V
V
V
SA
SA
SA
Input Reference Voltage
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
JTAG Test Mode Select
R
JTAG Test Data Output
8
SS
SS
SS
SS
DLL Disable when low
Power Supply ( 1.8 V )
JTAG Test Data Input
Output Echo Clock
JTAG Test Clock
DESCRIPTION
Address Inputs
3
Data Outputs
controls write to D27:D35.
No Connect
Input Clock
Data Inputs
Ground
V
D17
D16
Q16
Q15
D14
Q13
D12
Q12
D11
D10
Q10
S A
Q 9
S A
DDQ
9
TM
V
II b4 SRAM
SS
V
TMS
Q17
D15
Q14
D13
Q11
Q 7
D6
Q 4
D3
Q 1
D9
D0
10
REF
/SA*
Dec. 2003
Rev 2.0
TDI
C Q
Z Q
NOTE
Q 8
D8
D7
Q 6
Q 5
D5
D4
Q 3
Q 2
D2
D1
Q 0
11
1
2
3