HM1-6514B-9 INTERSIL [Intersil Corporation], HM1-6514B-9 Datasheet - Page 6

• Manufacturer Part Number: HM1-6514B-9
• Description: 1024 x 4 CMOS RAM
• Manufacturer: INTERSIL [Intersil Corporation]

Timing Waveforms
The write cycle is initiated by the falling edge of E (T = 0),
which latches the address information in the on-chip regis-
ters. There are two basic types of write cycles, which differ in
the control of the common data-in/data-out bus.
Case 1: E falls before W falls
The output buffers may become enabled (reading) if E falls
before W falls. W is used to disable (three-state) the outputs
so input data can be applied. TWLDV must be met to allow
the W signal time to disable the outputs before applying
input data. Also, at the end of the cycle the outputs may
become active if W rises before E. The RAM outputs and all
inputs will three-state after E rises (TEHQZ). In this type of
write cycle TWLEL and TEHWH may be ignored.
Case 2: E falls equal to or after W falls, and E rises before
REFERENCE
REFERENCE
TIME
TIME
or equal to W rising
-1
0
1
2
3
4
5
DQ
W
A
E
HIGH Z
H
H
TEHEL
E
L
L
-1
(Continued)
TAVEL
INPUTS
VALID ADD
0
W
H
X
X
X
X
L
TELWL
TELAX
FIGURE 2. WRITE CYCLE
A
X
V
X
X
X
X
V
TWLDV
TRUTH TABLE
1
HM-6514
TELWH
6-6
DQ
This E and W control timing will guarantee that the data out-
puts will stay disabled throughout the cycle, thus, simplifying
the data input timing. TWLEL and TEHWH must be met, but
TWLDV becomes meaningless and can be ignored. In this
cycle TDVWH and TWHDX become TDVEH and TEHDX. In
other words, reference data setup and hold times to the E
rising edge.
If a series of consecutive write cycles are to be performed,
W may be held low until all desired locations have been writ-
ten (an extension of Case 2).
V
Z
Z
Z
Z
Z
Z
TWLWH
TELEH
Case 1
Case 2
VALID DATA INPUT
TWLEH
TDVWH
Memory Disabled
Cycle Begins, Addresses are Latched
Write Period Begins
Data In is Written
Write Completed
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
TELEL
E falls before W
E falls after W and
E rises before W
IF
2
TWHEH
FUNCTION
OBSERVE
3
TWHDZ
TEHWH
TWLDV
TWLEL
HIGH Z
TEHEL
4
TEVAL
NEXT ADD
IGNORE
TWHDX
TWLDV
TWLEL
5