HM1-6516-9 INTERSIL [Intersil Corporation], HM1-6516-9 Datasheet

HM1-6516-9

Manufacturer Part Number

HM1-6516-9

Description

2K x 8 CMOS RAM

Manufacturer

INTERSIL [Intersil Corporation]

Datasheet

1.HM1-6516-9.pdf (6 pages)

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Download datasheet (36Kb)

March 1997

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Features

• Low Power Standby . . . . . . . . . . . . . . . . . . . 275 W Max

• Low Power Operation . . . . . . . . . . . . . 55mW/MHz Max

• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max

• Industry Standard Pinout

• Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V V

• TTL Compatible

• Static Memory Cells

• High Output Drive

• On-Chip Address Latches

• Easy Microprocessor Interfacing

Ordering Information

Pinouts

HM1-6516B-9

8403607JA

8403607ZA

GND

DQ0

DQ1

DQ2

120ns

TOP VIEW

(CERDIP)

HM-6516

HM1-6516-9

29102BJA

8403601JA

HM4-6516-9

8403601ZA

A10

DQ7

DQ6

DQ5

DQ4

DQ3

200ns

DQ0

Intersil Corporation 1999

14 15

TOP VIEW

16 17 18 19 20

HM-6516

(CLCC)

-55

TEMP. RANGE

-40

C to +125

C to +85

32 31 30

6-1

Description

The HM-6516 is a CMOS 2048 x 8 Static Random Access

Memory. Extremely low power operation is achieved by the

use of complementary MOS design techniques. This low

power is further enhanced by the use of synchronous circuit

techniques that keep the active (operating) power low, which

also gives fast access times. The pinout of the HM-6516 is

the popular 24 pin, 8-bit wide JEDEC standard, which allows

easy memory board layouts, ﬂexible enough to accommo-

date a variety of PROMs, RAMS, EPROMs, and ROMs.

The HM-6516 is ideally suited for use in microprocessor

based systems. The byte wide organization simpliﬁes the

memory array design, and keeps operating power down to a

minimum, because only one device is enabled at a time. The

address latches allow very simple interfacing to recent gen-

eration microprocessors which employ a multiplexed

address/data bus. The convenient output enable control also

simpliﬁes multiplexed bus interfacing by allowing the data

outputs to be controlled independent of the chip enable.

A10

DQ7

DQ6

CERDIP

CLCC

JAN#

SMD#

PACKAGE

HM-6516

DQ0 - DQ7 Data In/Data Out

A0 - A10

/GND

2K x 8 CMOS RAM

No Connect

Address Inputs

Chip Enable/Power Down

Ground

Power (+5V)

Write Enable

Output Enable

F24.6

J32.A

DESCRIPTION

File Number

PKG. NO.

2998.1

Related parts for HM1-6516-9

HM1-6516-9 Summary of contents

Page 1

... Industry Standard Pinout • Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V V • TTL Compatible • Static Memory Cells • High Output Drive • On-Chip Address Latches • Easy Microprocessor Interfacing Ordering Information 120ns 200ns HM1-6516B-9 HM1-6516-9 - 29102BJA 8403607JA 8403601JA - HM4-6516-9 8403607ZA 8403601ZA Pinouts HM-6516 (CERDIP) ...

Page 2

Functional Diagram A A10 A9 7 GATED LATCHED A8 ROW A7 ADDRESS A6 DECODER REGISTER HM-6516 128 x 128 MATRIX 128 GATED COLUMN ...

Page 3

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

AC Electrical Speciﬁcations V CC SYMBOL PARAMETER (1) TELQV Chip Enable Access Time (2) TAVQV Address Access Time (3) TELQX Chip Enable Output Enable Time (4) TWLQZ Write Enable Output Disable Time (5) TEHQZ Chip Enable Output Disable Time (6) ...

Page 5

Timing Waveforms (11) A (10) TEHEL E HIGH W (5) TEHQZ DQ G TIME REFERENCE -1 The address information is latched in the on-chip registers on the falling edge 0), minimum address setup and hold time ...

Page 6

The write cycle is initiated on the falling edge 0), which latches the address information in the on-chip registers write cycle performed where the output is not to become active, G ...

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