HM1-6516-9 INTERSIL [Intersil Corporation], HM1-6516-9 Datasheet - Page 5

• Manufacturer Part Number: HM1-6516-9
• Description: 2K x 8 CMOS RAM
• Manufacturer: INTERSIL [Intersil Corporation]

Timing Waveforms
The address information is latched in the on-chip registers
on the falling edge of E (T = 0), minimum address setup and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1), the outputs become
enabled but data is not valid until time (T = 2), W must
Timing Waveforms
REFERENCE
REFERENCE
TIME
TIME
DQ
DQ
W
W
A
G
G
E
A
E
HIGH
(Continued)
TEHQZ
(11)
(5)
TEHEL
-1
(10)
TEHEL
HIGH
(10)
-1
TAVEL
(11)
VALID ADD
TAVEL
VALID ADD
0
TELAX
0
(12)
TELAX
FIGURE 2. WRITE CYCLE
FIGURE 1. READ CYCLE
(12)
TELQX
(3)
TAVQV
(2)
HM-6516
TELQV
TELWH
(1)
(15)
6-5
TGLQV
TELEH
TGLQX
(6)
remain high throughout the read cycle. After the data has
been read, E may return high (T = 3). This will force the out-
put buffers into a high impedance mode at time (T = 4). G is
used to disable the output buffers when in a logical “1” state
(T = -1, 0, 3, 4, 5). After (T = 4) time, the memory is ready for
the next cycle.
(9)
1
TELEH
(7)
1
TWLWH
(9)
(13)
TDVWH
VALID DATA IN
(16)
TWLEH
(14)
TELEL
(18)
TELEL
(18)
2
VALID DATA OUT
2
3
TGHQZ
3
TEHQZ
TWHDX
(5)
(17)
TEHEL
(10)
4
TEHEL
(10)
4
TAVEL
NEXT ADD
(11)
(8)
TAVEL
(11)
NEXT
5
5
ADD