HM1-6518/883 INTERSIL [Intersil Corporation], HM1-6518/883 Datasheet - Page 7

• Manufacturer Part Number: HM1-6518/883
• Description: 1024 x 1 CMOS RAM
• Manufacturer: INTERSIL [Intersil Corporation]

NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
The write cycle is initiated by the falling edge of E which
latches the address information into the on chip registers.
The write portion of the cycle is defined as E, W, S1 and S2
being low simultaneously. W may go low anytime during the
cycle provided that the write enable pulse setup time
(TWLEH) is met. The write portion of the cycle is terminated
by the first rising edge of either E, W, S1 or S2. Data setup
and hold times must be referenced to the terminating signal.
If a series of consecutive write cycles are to be performed,
the W line may remain low until all desired locations have
been written. When this method is used, data setup and hold
times must be referenced to the rising edge of E.
Test Load Circuit
NOTE:
1. Test head capacitance includes stray and jig capacitance.
REFERENCE
TIME
-1
0
1
2
3
4
5
E
H
H
L
L
(NOTE 1) CL
S1
X
X
X
X
X
L
DUT
INPUTS
W
X
X
L
L
X
X
X
A
X
V
X
X
X
X
V
HM-6518/883
TRUTH TABLE
IOH
EQUIVALENT CIRCUIT
6-91
D
X
X
V
V
X
X
X
By positioning the W pulse at different times within the E low
time (TELEH), various types of write cycles may be
performed. If the E low time (TELEH) is greater than the W
pulse (TWLWH), plus an output enable time (TSLQX), a
combination read write cycle is executed. Data may be
modified an indefinite number of times during any write cycle
(TELEH).
The data input and data output pins may be tied together for
use with a common I/O data bus structure. When using the
RAM in this method allow a minimum of one output disable
time (TWLQZ) after W goes low before applying input data to
the bus. This will ensure that the output buffers are not
active.
OUTPUTS
+
-
Q
1.5V
Z
Z
Z
Z
Z
Z
Z
Memory Disabled
Cycle Begins, Addresses are Latched
Write Mode has Begun
Data is Written
Write Completed
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
IOL
FUNCTION