K4E151611 Samsung, K4E151611 Datasheet - Page 7

• Manufacturer Part Number: K4E151611
• Description: 1M x 16Bit CMOS Dynamic RAM with Extended Data Out
• Manufacturer: Samsung

K4E171611D, K4E151611D
K4E171612D, K4E151612D
NOTES
10.
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4.
5.
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7.
8.
9.
K4E17(5)1611(2)D Truth Table
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
Input voltage levels are Vih/Vil. V
Transition times are measured between V
Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.
Operation within the
If
Assumes that t
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
t
characteristics only. If
duration of the cycle. If
modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions
is satisfied, the condition of the data out is indeterminate.
Either
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
Operation within the
If
WCS
RAS
t
t
H
L
L
L
L
L
L
L
L
RCD
RAD
,
t
t
RWD
is greater than the specified
is greater than the specified
RCH
,
or
t
LCAS
CWD
t
RCD
RRH
X
H
H
H
L
L
L
L
L
,
t
AWD
must be satisfied for a read cycle.
t
t
RCD
t
RCD
RAD
t
WCS
and
t
CWD
(max).
(max) limit insures that
(max) limit insures that
UCAS
X
H
H
H
L
L
L
L
L
t
t
WCS
CPWD
t
CWD
IH
(min), the cycle is an early write cycle and the data output will remain high impedance for the
(min) and V
(min),
are non restrictive operating parameters. They are included in the data sheet as electrical
t
t
RCD
RAD
(max) limit, then access time is controlled by
W
(max) limit, then access time is controlled exclusively by
H
H
H
H
X
X
L
L
L
t
IH
RWD
(min) and V
IL
t
(max) are reference levels for measuring timing of input signals.
RWD
t
t
RAC
RAC
OE
(min),
H
H
H
H
X
X
L
L
L
(max) can be met.
(max) can be met.
IL
(max) and are assumed to be 2ns for all inputs.
t
AWD
DQ0 - DQ7
t
AWD
DQ-OUT
DQ-OUT
DQ-IN
DQ-IN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
(min) and
-
t
t
RAD
RCD
(max) is specified as a reference point only.
(max) is specified as a reference point only.
t
CPWD
t
AA
DQ8-DQ15
DQ-OUT
DQ-OUT
.
t
DQ-IN
DQ-IN
CPWD
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
(min), then the cycle is a read-
t
CAC
CMOS DRAM
.
Word Read
Word Write
Byte Read
Byte Read
Byte Write
Byte Write
Standby
Refresh
STATE
oh
-
or V
ol
.