HT48C10 HOLTEK [Holtek Semiconductor Inc], HT48C10 Datasheet
HT48C10
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HT48C10 Summary of contents
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... ROM and RAM, as well as bit number, counter number, I/O line number, and different level subroutine nesting. Roughly speaking, the HT48C10 is a microcontroller with most economic features and the HT48C70 is one with the most features of the four micro- controllers. ...
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... I/O Pull-high Mask version SYS 400k~4MHz No 400k~4MHz Yes 400k~4MHz No 400k~4MHz Yes 400k~4MHz Yes 400k~4MHz No 2 HT48C70 2.4V~5. Crystal/ 224 8 (20H~FFH 400kHz~8MHz HT48C10 HT48C10 HT48C30 HT48C30 HT48C50 HT48C50 25th May ’99 ...
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Block Diagram of HT48C70 HT48CXX/HT48RXX 3 25th May ’99 ...
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Pin Assignment HT48CXX/HT48RXX 4 25th May ’99 ...
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Note: For the dice form, the TMR0 and TMR1 pads have to be bonded to VDD or VSS if the TMR0 and/or TMR1 pad are not used. The (TMR0) INT indicates that the TMR0 pad should be bonded to the ...
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... Pin Description of HT48C10 Mask Pin Name I/O Option Bidirectional 8-bit input/output ports Wake-up Each bit can be configured as a wake-up input by mask option. PA0~PA7 I/O Pull-high Software instructions determine the CMOS output or schmitt or None trigger input with or without pull high resistor (by mask option). Bidirectional 8-bit input/output ports ...
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Pin Description of HT48C30 Mask Pin Name I/O Option Bidirectional 8-bit input/output ports Wake-up Each bit can be configured as a wake-up input by mask option. PA0~PA7 I/O Pull-high Software instructions determine the CMOS output or schmitt or None trigger ...
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Pin Description of HT48C50 Mask Pin Name I/O Option Bidirectional 8-bit input/output ports Wake-up Each bit can be configured as a wake-up input by mask option. PA0~PA7 I/O Pull-high Software instructions determine the CMOS output or schmitt or None trigger ...
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Pin Description of HT48C70 Mask Pin Name I/O Option Bidirectional 8-bit input/output ports Wake-up Each bit can be configured as a wake-up input by mask option. PA0~PA7 I/O Pull-high Software instructions determine the CMOS output or schmitt or None trigger ...
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... D.C. Characteristics Symbol Parameter V Operating Voltage DD Operating Current I DD1 (HT48C10 Crystal OSC) Operating Current I DD2 (HT48C10 RC OSC) Operating Current I DD3 (HT48C30 Crystal OSC) Operating Current I DD4 (HT48C30 RC OSC) Operating Current I DD5 (HT48C50 Crystal OSC) Operating Current ...
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Symbol Parameter Input Low Voltage for I ports Input High Voltage for I Ports Input Low Voltage V IL1 (TMR, TMR0, TMR1, INT) Input High Voltage V IH1 (TMR, TMR0, TMR1, INT) V Input Low Voltage ...
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A.C. Characteristics Symbol Parameter f System Clock (Crystal OSC) SYS1 f System Clock (RC OSC) SYS2 Timer I/P Frequency f TIMER (TMR, TMR0, TMR1) t Watchdog Oscillator WDTOSC Watchdog Time-out t WDT1 Period (RC) Watchdog Time-out Period t WDT2 (System ...
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... Program counter – PC The program counter (PC different sizes ranging from 10 bits to 13 bits according to the microcontroller selected (10 bits for the HT48C10; 11 bits for the HT48C30; 12 bits for the HT48C50; 13 bits for the HT48C70). It con- HT48CXX/HT48RXX trols a sequence in which the instructions stored in the program ROM are executed ...
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... HT48C70 HT48CXX/HT48RXX Program memory HT48C50/HT48C70. If the timer interrupt re- sults from a timer/event counter overflow of the HT48C10/HT48C30 or a timer/event counter 0 overflow of the HT48C50/HT48C70, and the interrupt is enabled, and the stack is not full, the program begins execution at loca- tion 008H. Contents of Program Counter (m bits) 14 25th May ’ ...
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... PC. The stack can be organized into levels according to the microcontroller selected (2 levels for the HT48C10/HT48C30, 4 levels for the HT48C50, 8 levels for the HT48C70). The register is nei- ther part of the data nor part of the program, and is neither readable nor writeable. Any acti- vated level is indexed by a stack pointer (SP) and is neither readable nor writeable ...
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... Data memory – RAM The data memory (RAM) is composed of bits ranging from 81 8, 113 8, 184 8, or 255 8, de- pending on the microcontroller chosen (HT48C10/ HT48C30/HT48C50/HT48C70 divided into two functional groups, i.e., special function registers and general purpose data memory ( 160 8, or 224 8 bits, depending on the microcontroller selected (HT48C10/ HT48C30/HT48C50/HT48C70) ...
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... The function of data movement between two indirect addressing registers is not supported. The memory pointer register MP of the HT48C10/HT48C30 or MP0 and MP1 of the HT48C50/HT48C70 are of 7 bits or 8 bits wide respectively, and can be used to access the RAM HT48CXX/HT48RXX by combining the corresponding indirect ad- dressing registers ...
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... The inter- rupt request flag (EIF) and EMI bits will also be cleared to disable other interrupts. Of the four microcontrollers, the internal timer/event counter interrupt of the HT48C10/ HT48C30 is initialized by setting the timer/ Function Status register 18 ...
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INTC), that is caused by a timer overflow. When the interrupt is enabled, and the stack is not full, and the TF bit is set, a subroutine call to location 08H ...
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... These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (TF, EIF of the HT48C10/HT48C30 or T0F, T1F, EIF of the HT48C50/HT48C70) are set, they will remain in the INTC register until the inter- rupts are all serviced or cleared by a software instruction ...
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If the internal WDT oscillator (RC oscillator with a period normally) is selected first divided by 256 (8 stages) to derive a nomi- nal time-out period of about 20ms. This time- out period may vary ...
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WDT overflow. An external reset may cause device initialization, and the WDT overflow performs a “warm reset”. Examining the TO and PD flags, the reason for chip reset ...
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... Of the HT48C10/HT48C30, there are two regis- ters related to the timer/event counter, i.e., TMR ([0DH]) and TMRC ([0EH]). There are two physical registers mapped to the TMR location. ...
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The states of the special function registers are summarized in the following table: WDT time-out Reset Register (normal (power on) operation) TMR1H xxxx xxxx uuuu uuuu TMR1L xxxx xxxx uuuu uuuu TMR1C 00-0 1--- 00-0 1--- TMR0H xxxx xxxx uuuu ...
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... HT48C50 (TMR1 FFFFH of the HT48C50 (TMR0)/HT48C70 overflow occurs, the counter is reloaded from the timer/ event counter preload register and generates the corresponding interrupt request flag TF (bit 5 of INTC) of the HT48C10/HT48C30 or T0F/T1F (bit 5/6 of INTC) of the HT48C50/ HT48C70 at the same time. Function 25 25th May ’99 ...
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... To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC of the HT48C10/ HT48C30 or bit 4 of TMR0C/TMR1C of the HT48C50/HT48C70) should be set the pulse width measurement mode, the TON will be cleared automatically after the measure- ment cycle is complete ...
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PA to PD, which are mapped to the [12H], [14H], [16H], or 18H], respectively. Finally, the HT48C70 contains 56 bidirectional input/out- put lines, labeled from PA to PG, which are mapped to the RAM of ...
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Application Circuits of HT48C70 f (kHz SYS 8000 0 0 6000 0 0 4000 0 0 3580 0 0 2000 0 0 1000 0 0 640 300pF 300pF 480 300pF 300pF 455 300pF 300pF 400 300pF 300pF HT48CXX/HT48RXX ...
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Instruction Set Summary Mnemonic Description Arithmetic ADD A,[m] Add data memory to ACC ADDM A,[m] Add ACC to data memory ADD A,x Add immediate data to ACC ADC A,[m] Add data memory to ACC with carry ADCM A,[m] Add ACC ...
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Mnemonic Description Rotate RRA [m] Rotate data memory right with result in ACC RR [m] Rotate data memory right RRCA [m] Rotate data memory right through carry with result in ACC RRC [m] Rotate data memory right through carry RLA ...
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... Swap nibbles of data memory SWAPA [m] Swap nibbles of data memory with result in ACC HALT Enter power down mode Notes: x: 8-bit immediate data m: 7-bit data memory address for HT48C10/HT48C30 m: 8-bit data memory address for HT48C50/HT48C70 A: Accumulator i: 0~7 number of bits A: Accumulator i: 0~7 number of bits addr: Program memory address : Flag(s) is affected – ...
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Instruction Definition Add data memory and carry to the accumulator ADC A,[m] Description The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. Operation ACC ACC+[m]+C Affected flag(s) TC2 ...
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ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TC2 TC1 TO – – ...
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CALL addr Subroutine call Description The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then ...
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CLR WDT1 Preclear watchdog timer Description The TD, PD flags, WDT and the WDT Prescaler has cleared (re-counting from zero), if the other preclear WDT instruction has been executed. Only execu- tion of this instruction without the other preclear instruction ...
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CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1’s comple- ment). Bits which previously contained a one are changed to zero and vice-versa. The complemented result ...
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DECA [m] Decrement data memory and place result in the accumulator Description Data in the specified data memory is decremented by one, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC [m]–1 Affected ...
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JMP addr Directly jump Description The contents of the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Operation PC addr Affected flag(s) TC2 TC1 TO – – MOV A,[m] Move data memory ...
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OR A,[m] Logical OR accumulator with data memory Description Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. Operation ACC ACC “OR” [m] ...
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RET A,x Return and place immediate data in the accumulator Description The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Operation PC Stack ACC x Affected flag(s) TC2 TC1 TO – ...
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RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated one bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit ...
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RRA [m] Rotate right-place result in the accumulator Description Data in the specified data memory is rotated one bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory ...
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SBC A,[m] Subtract data memory and carry from the accumulator Description The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumu- lator. Operation ACC ACC+[m]+C ...
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SET [m] Set data memory Description Each bit of the specified data memory is set to one. Operation [m] FFH Affected flag(s) TC2 TC1 TO – – SET [m].i Set bit of data memory Description Bit “i” of the specified ...
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SNZ [m].i Skip if bit “i” of the data memory is not zero Description If bit “i” of the specified data memory is not zero, the next instruction is skipped. If bit “i” of the data memory is not zero, ...
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SWAP [m] Swap nibbles within the data memory Description The low-order and high-order nibbles of the specified data memory (one of the data memories) are interchanged. Operation [m].3~[m].0 [m].7~[m].4 Affected flag(s) TC2 TC1 TO – – SWAPA [m] Swap data ...
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SZ [m].i Skip if bit “i” of the data memory is zero Description If bit “i” of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced ...
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XORM A,[m] Logical XOR data memory with the accumulator Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The zero flag is affected. Operation [m] ...
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Characteristic Curves Figure A: Typical RC oscillator frequency vs. temperature Figure B: Typical RC oscillator frequency vs. V HT48CXX/HT48RXX DD 49 25th May ’99 ...
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Figure HT48CXX/HT48RXX Figure 25th May ’99 ...
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Figure HT48CXX/HT48RXX Figure 25th May ’99 ...
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Figure Max HT48CXX/HT48RXX Figure Min 25th May ’99 ...
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Figure vs –40°C to +85°C IH HT48CXX/HT48RXX 53 25th May ’99 ...
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Figure J: Typical I vs. V watchdog enabled STB DD Figure K: Typical I vs. V watchdog disabled STB DD HT48CXX/HT48RXX 54 25th May ’99 ...
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Figure L: Maximum I vs. Frequency (external clock – HT48CXX/HT48RXX 55 25th May ’99 ...
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HT48CXX/HT48RXX 56 25th May ’99 ...
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Figure M: Operating voltage-Operating frequency (crystal) HT48CXX/HT48RXX 57 25th May ’99 ...
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Figure N: Operating voltage vs. T WDT HT48CXX/HT48RXX 58 25th May ’99 ...
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Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International ...