HT48C50- HOLTEK [Holtek Semiconductor Inc], HT48C50- Datasheet

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... General Description The device is an 8-bit high performance RISC-like microcontroller designed for multi- ple I/O product applications. The device is par- ticularly suitable for use in products such as HT48C50-1 8-Bit Microcontroller 4096´15 program memory ROM · · 160´8 data memory RAM · ...

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... Block Diagram Preliminary 2 HT48C50-1 June 14, 2000 ...

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... Pin Assignment Pad Assignment * The IC substrate should be connected to VSS in the PCB layout artwork. Preliminary 3 HT48C50-1 June 14, 2000 ...

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... Timer/event counter 0 schmitt trigger input (without pull-high resistor) Bidirectional I/O lines. Software instructions deter- mine the CMOS output or schmitt trigger input with pull-high resistor (determined by pull-high options). Timer/event counter 1 schmitt trigger input (without pull-high resistor) Schmitt trigger reset input. Active low Positive power supply 4 HT48C50-1 June 14, 2000 ...

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... No load, f =4MHz SYS 5V ¾ 3V ¾ No load, f =4MHz SYS 5V ¾ No load, f =8MHz 5V ¾ SYS 3V ¾ No load, system HALT 5V ¾ 3V ¾ No load, system HALT 5V ¾ 5 HT48C50-1 Ta=25°C Typ. Max. Unit ¾ 5.5 V ¾ 5 ¾ ¾ ...

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... Without WDT prescaler HT48C50-1 Typ. Max. Unit ¾ ¾ mA 0.2V ¾ ¾ 0.4V ¾ ¾ ¾ ¾ ...

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... Once the condition is met, the next in- structio n, fetche d d uring the curr ent instruction execution, is discarded and a dummy cycle replaces it to get the proper in- struction. Otherwise proceed with the next in- struction. Execution flow 7 HT48C50-1 t 1024 ¾ SYS 7.812 ¾ ms ¾ ...

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... PC Program counter S11~S0: Stack register bits @7~@0: PCL bits 8 HT48C50 June 14, 2000 ...

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... Table Location * Table location P11~P8: Current program counter bits 9 HT48C50 June 14, 2000 ...

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... Reading location 00H (02H) itself indirectly will return the result 00H. Writing indirectly results in no operation. The memory pointer registers (MP0 and MP1) are 8-bit registers. 10 HT48C50 June 14, 2000 ...

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... If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Function Status register 11 HT48C50-1 June 14, 2000 ...

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... The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The internal timer/even counter 1 interrupt is initialized by setting the timer/event counter 1 interrupt request flag (T1F;bit 6 of INTC), caused by a timer 1 overflow. When the inter- Function INTC register 12 HT48C50-1 June 14, 2000 ...

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... RC oscillator, the external Crystal oscillator and the internal RC oscillator, which are determined by mask op- tion. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. Watchdog Timer 13 HT48C50-1 June 14, 2000 ...

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... WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instruction and a "HALT" in- struction. The software instruction include "CLR WDT" and the other set - "CLR WDT1" and "CLR WDT2". Of these two types of instruc- 14 HT48C50-1 Division Ratio 1:1 1:2 1:4 1:8 1:16 ...

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... TO PD RESET Conditions 0 0 RES reset during power- RES reset during normal operation 0 1 RES wake-up HALT WDT time-out during normal 1 u operation 1 1 WDT wake-up HALT Note: "u" stands for "unchanged" 15 HT48C50-1 (sys- SYS June 14, 2000 ...

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... Reset configuration Preliminary The functional unit chip reset status are shown below. PC 000H Interrupt Disable Prescaler Clear Clear. After master reset, WDT WDT begins counting Timer/event Off Counter Input/output Input mode Ports Points to the top of SP the stack 16 HT48C50-1 June 14, 2000 ...

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... HT48C50-1 WDT Time-out (HALT)* uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uu-u u--- 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ...

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... SYS RTC / SYS RTC / SYS RTC / /16 SYS RTC / /32 SYS RTC / /64 SYS RTC /128 or f /128 SYS RTC /256 or f /256 SYS RTC TMR0C register Timer/event counter 0 18 HT48C50-1 June 14, 2000 ...

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... But if the timer/event counter 0/1 is turned on, data writ- ten to it will only be kept in the timer/event counter 0/1 preload register. The timer/event counter 0/1 will still operate until overflow oc- curs (a timer/event counter 0/1 reloading will oc- 19 HT48C50-1 June 14, 2000 ...

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... The latter is pos- sible in the "read-modify-write" instruction. For output function, CMOS is the only configu- ration. These control registers are mapped to locations 13H, 15H, 17H, 19H and 1FH. Function TMR1C register Timer/event counter 1 20 HT48C50-1 June 14, 2000 ...

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... PB0/PB1 are shown below ² data HT48C50 June 14, 2000 ...

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... The LVR uses the ²OR² function with the ex- ternal RES signal to perform chip reset. The relationship between V shown below. Note the voltage range for proper chip OPR operation at 4MHz system clock. Input/output ports 22 HT48C50-1 and LVR June 14, 2000 ...

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... PA, PB, PC, PD CMOS/SCHMITT input 7 PA, PB, PC, PD, PG pull-high enable/disable 8 BZ/BZ enable/disable 9 LVR enable/disable 10 LVR voltage: 2.2V or 3.3V System oscillator 11 Ext. RC, Ext.crystal, Int.RC+RTC or Int.RC+PC3/PC4 12 Int.RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz Preliminary Low voltage reset Option /RTCOSC/disable TID or RTCOSC SYS /4 or RTCOSC SYS 23 HT48C50-1 June 14, 2000 ...

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... VDD is stable and remains within a valid operating voltage range before bringing RES to high. Preliminary Crystal or ceramic resonator for multiple I/O applications Note: C1=C2=300pF if f <1MHz SYS Otherwise, C1=C2=0 Internal RC oscillator with RTC for multiple I/O applications HT48C50-1 June 14, 2000 ...

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... Increment & Decrement INCA [m] Increment data memory with result in ACC INC [m] Increment data memory DECA [m] Decrement data memory with result in ACC DEC [m] Decrement data memory Preliminary Instruction Cycle 1( HT48C50-1 Flag Affected 1 Z,C,AC,OV (1) Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) Z,C,AC,OV 1 Z,C,AC,OV Z,C,AC,OV (1) C ...

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... Return from subroutine RET A,x Return from subroutine and load immediate data to ACC RETI Return from interrupt Preliminary Instruction Cycle HT48C50-1 Flag Affected 1 None (1) None None (1) None None (1) None 1 None ...

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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared. Otherwise the TO and PD flags remain unchanged. Preliminary Instruction Cycle HT48C50-1 Flag Affected (1) None (1) None 1 None (1) None (1) ...

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... Preliminary ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö 28 HT48C50-1 June 14, 2000 ...

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... Preliminary ¾ ¾ Ö Ö Ö Ö ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 29 HT48C50-1 June 14, 2000 ...

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... Preliminary ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 30 HT48C50-1 June 14, 2000 ...

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... Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] ¬ [m] Affected flag(s) TC2 TC1 ¾ ¾ Preliminary ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 31 HT48C50-1 June 14, 2000 ...

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... Data in the specified data memory is decremented by 1. Operation [m] ¬ [m]-1 Affected flag(s) TC2 TC1 ¾ ¾ Preliminary ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ Ö ¾ ¾ 32 HT48C50-1 June 14, 2000 ...

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... Preliminary ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 33 HT48C50-1 June 14, 2000 ...

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... ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 34 HT48C50-1 June 14, 2000 ...

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... Preliminary ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 35 HT48C50-1 June 14, 2000 ...

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... Preliminary ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 36 HT48C50-1 June 14, 2000 ...

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... Affected flag(s) TC2 TC1 ¾ ¾ Preliminary ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ 37 HT48C50-1 June 14, 2000 ...

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... ACC.7 ¬ ¬ [m].0 Affected flag(s) TC2 TC1 ¾ ¾ Preliminary ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö 38 HT48C50-1 June 14, 2000 ...

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... Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1) Affected flag(s) TC2 TC1 ¾ ¾ Preliminary ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö ¾ ¾ ¾ ¾ ¾ ¾ 39 HT48C50-1 June 14, 2000 ...

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... Preliminary ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 40 HT48C50-1 June 14, 2000 ...

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... Preliminary ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö 41 HT48C50-1 June 14, 2000 ...

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... Preliminary ¾ ¾ Ö Ö Ö Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 42 HT48C50-1 June 14, 2000 ...

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... Preliminary ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 43 HT48C50-1 June 14, 2000 ...

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... ACC ¬ ACC "XOR" x Affected flag(s) TC2 TC1 ¾ ¾ Preliminary ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 44 HT48C50-1 June 14, 2000 ...

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... Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. HT48C50-1 45 June 14, 2000 ...