HT48R01N-1 HOLTEK [Holtek Semiconductor Inc], HT48R01N-1 Datasheet
HT48R01N-1
Related parts for HT48R01N-1
HT48R01N-1 Summary of contents
Page 1
... Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Small Package 8-Bit OTP MCU 6-level subroutine nesting All instructions executed in one or two instruction cycles ...
Page 2
... HT46R01N HT48R01B HT48R01N Block Diagram The following block diagram illustrates the main functional blocks. Pin Assignment Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 8-bit Time HIRC RTC A/D Timer Base (MHz) (LXT 4/8/12 12-bit 12-bit ...
Page 3
... OSC: Oscillator pin PWR: Power *: AVDD is the ADC power supply and is bonded together internally with VDD while AVSS is the ADC ground pin and is bonded together internally with VSS. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 I/T O/T Description ST CMOS General purpose I/O. Register enabled pull-up and wake-up. ...
Page 4
... OSC: Oscillator pin PWR: Power *: AVDD is the ADC power supply and is bonded together internally with VDD while AVSS is the ADC ground pin and is bonded together internally with VSS. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 I/T O/T Description ST CMOS General purpose I/O. Register enabled pull-up and wake-up. ...
Page 5
... CMOS: CMOS output NMOS: NMOS output OSC: Oscillator pin PWR: Power Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 O/T Description CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS PFD output CMOS General purpose I/O. Register enabled pull-up and wake-up. ...
Page 6
... CMOS: CMOS output NMOS: NMOS output OSC: Oscillator pin PWR: Power Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 O/T Description CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS PFD output CMOS General purpose I/O. Register enabled pull-up and wake-up. ...
Page 7
... Input Low Voltage (RES) IL2 V Input High Voltage (RES) IH2 V Low Voltage Reset 1 LVR1 V Low Voltage Reset 2 LVR2 V Low Voltage Reset 3 LVR3 Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH Test Conditions Min. V Conditions DD f =4MHz 2 ...
Page 8
... PA7 Sink Current OL2 R Pull-high Resistance PH Note: The standby current ( and I STB1 STB3 A.C. Characteristics Symbol Parameter f System Clock SYS System Clock f HIRC (HIRC) Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Test Conditions Min. V Conditions =0. =0. ...
Page 9
... Low Voltage Width to Reset LVR t Reset Delay Time RSTD Note =1/f SYS SYS 2. *For the resistor tolerance will influence the frequency a precision resistor is recommended. ERC Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Test Conditions Min. V Conditions DD 5V Ta=25 C, R=120k * 2% 5V Ta=0~70 C, R=120k * 5% Ta R=120k * 2 ...
Page 10
... Parameter VDD Start Voltage to Ensure V POR Power-on Reset VDD Rise Rate to Ensure RR VDD Power-on Reset Minimum Time for VDD to remain t POR Ensure Power-on Reset POR Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Test Conditions Min. V Conditions ...
Page 11
... RC oscillator is subdivided into four in- ternally generated non-overlapping clocks, T1~T4. The Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle ...
Page 12
... The acti- vated level is indexed by the Stack Pointer, SP, and is Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 neither readable nor writeable subroutine call or in- terrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a sub- ...
Page 13
... This internal vector is used by the Timer/Event Coun- ters Timer/Event Counter overflow occurs, the Program Memory Structure Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 program will jump to its respective location and begin execution if the associated Timer/Event Counter inter- rupt is enabled and the stack is not full. A/D interrupt vector This internal vector is used by the A/D converter ...
Page 14
... Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 the Program Memory address 306H or 6 locations af- ter the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the TABRDC [m] instruction is being used ...
Page 15
... The Data Memory can also be accessed through the memory pointer registers. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and ...
Page 16
... The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Memory Pointers - MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are pro- vided. These Memory Pointers are physically imple- ...
Page 17
... C is also affected by a rotate through carry instruction. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag ...
Page 18
... PWM. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 System Control Registers - CTRL0, CTRL1 These registers are used to provide control over various internal functions. Some of these include the PFD con- trol, PWM control, certain system clock options, the LXT ...
Page 19
... CTRL0 Register - HT48R01B-1/HT48R01N-1 Bit 7 6 Name PFDCS R/W R/W POR 0 Bit 7 unimplemented, read as 0 Bit 6 PFDCS: PFD clock source selection 0: Timer 0 1: Timer 1 Bit 5~3 unimplemented, read as 0 Bit 2 PFDC: I/O or PFD selection 0: I/O 1: PFD Bit 1 LXTLP: LXT oscillator low power control function 0: LXT oscillator quick start-up mode ...
Page 20
... Also there is an internal 15kHz RC oscillator named LIRC oscillator used as the clock source for the Crystal/Resonator Oscillator - HXT Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 WDT function. More details are described in the accom- panying sections. External Crystal/Resonator Oscillator - HXT The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feed- back for oscillation ...
Page 21
... required. For the device P the LXT oscillator must be used together with the HIRC oscillator. External LXT Oscillator Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 LXT Oscillator C1 and C2 Values Crystal Frequency C1 32768Hz 8pF Note and C2 values are for guidance only =5M~10M is recommended ...
Page 22
... The ac- companying tables shows the relationship between the CLKMOD bit, the HALT instruction and the high/low fre- quency oscillators. The CLMOD bit can change normal or Slow Mode. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 OSC1/OSC2 Configuration Operating Mode HXT Normal Run ...
Page 23
... TO and PDF flags. The PDF flag is cleared by a Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out ...
Page 24
... SYS Watchdog Timer will cease to function. For systems that Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 operate in noisy environments, using the LIRC or the LXT as the clock source is therefore the recommended choice. The division ratio of the prescaler is determined by bits 0, 1 and 2 of the WDTS register, known as WS0, WS1 and WS2 ...
Page 25
... LVR, where a full reset, similar to the RES reset is imple- mented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and ex- ternally: Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N WS2 R/W 1 Power-on Reset ...
Page 26
... Note power-on delay, typical time=100ms RSTD Low Voltage Reset Timing Chart Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 will ignore the low supply voltage and will not perform a reset function. The actual V LVR lected via configuration options. Watchdog Time-out Reset during Normal Operation ...
Page 27
... CTRL0 CTRL1 PWM Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Condition After RESET RES or LVR WDT Time-out Reset (Normal Operation ...
Page 28
... CTRL1 Note: - not implemented u means unchanged x means unknown Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 RES or LVR WDT Time-out Reset (Normal Operation ...
Page 29
... PAPUn/PBPUn: Pull-high function enable 0: disable 1: enable Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 tors are implemented using weak PMOS transistors. Note that pin PA7 does not have a pull-high resistor se- lection. Port A Wake-up If the HALT instruction is executed, the device will enter the Sleep Mode, where the system clock will stop result- ing in power being conserved, a feature that is important for battery and other low-power applications ...
Page 30
... I/O function still remains. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 PFD Output The PFD function output is pin-shared with an I/O pin. The output function of this pin is chosen using the CTRL0 register. Note that the corresponding bit of the port control register, must setup the pin as an output to enable the PFD output ...
Page 31
... Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Generic Input/Output Ports PA7 NMOS Input/Output Port PA7 NMOS Input/Output Port 31 June 9, 2011 ...
Page 32
... Reading from this register Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer Control Register which defines the timer options and deter- mines how the timer used ...
Page 33
... Note: If PWM is enabled, then f comes from f TP Clock Structure for Timer/PWM/Time Base 8-bit Timer/Event Counter 0 Structure 8-bit Timer/Event Counter 1 Structure Note: If PWM0 is enabled, then f Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 and the T0S bit will have no effect. SYS comes from f (ignore T0S) TP SYS 33 June 9, 2011 ...
Page 34
... TP 010 011 100: f /16 TP 101: f /32 TP 110: f /64 TP 111: f /128 TP Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N T0S T0ON T0EG T0PSC2 R/W R/W R/W R which is provided for Timer 0, the Time-Base and TP will be selected, overriding the T0S selection. SYS 34 1 ...
Page 35
... Event counter active edge selection 0: count on raising edge 1: count on falling edge Pulse Width Capture active edge selection 0: start counting on falling edge, stop on rasing edge 1: start counting on raising edge, stop on falling edge Bit 2~0 unimplemented, read as 0 Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N T1S T1ON T1EG R/W R/W ...
Page 36
... Select Bits for the Timer Mode Event Counter Mode Timing Chart (TnEG=1) Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 In this mode the internal clock is used as the timer clock. The timer input clock source is f oscillator depending upon whether the Timer/Event Counter 0 or Timer/Event Counter 1 is selected. For ...
Page 37
... Timer/Event Counter will start counting until the external Pulse Width Capture Mode Timing Chart (TnEG=0) Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 timer pin returns to its original high level. At this point the enable bit will be automatically reset to zero and the Timer/Event Counter will stop counting. If the Active ...
Page 38
... Timer/Event Counter input. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 PFD Function Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller ...
Page 39
... When the Time Base time out, a Time Base interrupt signal will be generated. It should be noted that as the Time Base clock source is the same as the Timer/Event Counter clock source, care should be taken when programming. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 rupt request flag should first be set high before issuing the HALT instruction to enter the Sleep Mode. Timer Program Example ...
Page 40
... The 8-bit PWM register value, which repre- sents the overall duty cycle of the PWM waveform, is di- Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 vided into two groups. The first group which consists of bit2~bit7 is denoted here as the DC value. The second group which consists of bit0~bit1 is known as the AC value ...
Page 41
... Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 6+2 PWM Mode PWM Register for 6+2 Mode 7+1 PWM Mode PWM Register for 7+1 Mode 41 June 9, 2011 ...
Page 42
... PWM output_ pin ; PA4 forced low Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 the PWM data to appear on the pin. Writing a zero value will disable the PWM output function and force the out- put low. In this way, the Port data output registers can be used as an on/off control for the PWM function ...
Page 43
... ADRH, utilises its full 8-bit contents. The low byte regis- ter utilises only 4 bit of its 8-bit contents as it contains only the lowest bits of the 12-bit converted value. In the following table, D0~D11 is the A/D conversion data result bits. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Bit Bit Bit Register 7 6 ...
Page 44
... ADCS2~ADCS0 : Select A/D converter clock source 000: system clock/2 001: system clock/8 010: system clock/32 011: undefined, can t be used. 100: system clock 101: system clock/4 110: system clock/16 111: undefined, can t be used. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N ...
Page 45
... Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 The A/D converter overall on/off control is a function of both the ADONB bit in the ACSR register and the PCRn bits in the ADCR register as shown in the table. Either the ADONB bit cleared to zero or the PCRn bits set to a zero value will switch off the A/D converter ...
Page 46
... Note that this bit should have been originally set Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Step 7 To check when the analog to digital conversion pro- cess is complete, the EOCB bit in the ADCR register can be polled. The conversion process is complete when this bit goes low ...
Page 47
... Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 A/D Conversion Timing Ideal A/D Transfer Function 47 June 9, 2011 ...
Page 48
... ADF reti Note: To power off ADC module necessary to set ADONB Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 ; disable ADC interrupt ; select A/D clock and ADONB=0 SYS ; setup ADCR register to configure Port as A/D inputs ; and select AN0 to be connected to the A/D converter ...
Page 49
... The Program Counter will * A/D converter interrupt is for HT46R01B-1/HT46R01N-1 only. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector ...
Page 50
... Timer/Event Counter 1 Overflow Time Base Overflow Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 In cases where both external and internal interrupts are enabled and where an external and internal interrupt oc- curs simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences ...
Page 51
... Bit 4 ADF: A/D Conversion interrupt request flag 0: inactive 1: active Bit 3~2 unimplemented, read as 0 Bit 1 TBE: Time base event interrupt enable 0: disable 1: enable Bit 0 ADE: A/D Conversion interrupt enable 0: disable 1: enable Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N T0F INTF T1E T0E R/W R/W R/W R ...
Page 52
... For a time base interrupt to occur the global interrupt en- able bit EMI and the corresponding interrupt enable bit TBE, must first be set. An actual Time Base interrupt will take place when the time base request flag TBF is set, a Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N TBF ...
Page 53
... Note: LXT oscillator must be selected by OSC configuration option if WDT clock source is from LXT. 3 CLRWDT instructions instructions 4 System oscillator configuration: HXT, HIRC, ERC, HIRC + LXT 5 LVR function: enable or disable 6 LVR voltage: 2.1V, 3.15V or 4.2V 7 RES or PA7 pin function 8 Internal RC: 4MHz, 8MHz or 12MHz Application Circuits Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Options /4 SYS 53 June 9, 2011 ...
Page 54
... Within the Holtek microcontroller instruction set are a range of add and Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
Page 55
... Decrement Data Memory with result in ACC DEC [m] Decrement Data Memory Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro- magnetic environments ...
Page 56
... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Description 56 Cycles Flag Affected 1 ...
Page 57
... ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 57 June 9, 2011 ...
Page 58
... CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 addr 58 June 9, 2011 ...
Page 59
... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N June 9, 2011 ...
Page 60
... No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 addr 60 June 9, 2011 ...
Page 61
... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Stack Stack Stack [m]. 0~6) 61 June 9, 2011 ...
Page 62
... Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 [m]. 0~6) 62 June 9, 2011 ...
Page 63
... Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 [ June 9, 2011 ...
Page 64
... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 0 [m] [ June 9, 2011 ...
Page 65
... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 65 June 9, 2011 ...
Page 66
... ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 66 June 9, 2011 ...
Page 67
... MSOP Outline Dimensions Symbol Symbol Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Dimensions in inch Min. Nom. 0.000 0.030 0.033 0.007 0.118 0.193 0.118 0.020 0.016 0.024 0.037 0 Dimensions in mm Min. Nom. 0.00 0.75 0.85 0.17 3.00 4.90 3.00 0.50 0.40 ...
Page 68
... NSOP (150mil) Outline Dimensions MS-012 Symbol Symbol Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Dimensions in inch Min. Nom. 0.228 0.150 0.012 0.386 0.050 0.004 0.016 0.007 0 Dimensions in mm Min. Nom. 5.79 3.81 0.30 9.80 1.27 0.10 0.41 0. Max. 0.244 0.157 ...
Page 69
... Product Tape and Reel Specifications Reel Dimensions SOP 16N (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Dimensions in mm 330.0 1.0 100.0 1.5 +0.5/-0.2 13.0 2.0 0.5 +0.3/-0.2 16.8 22.2 0.2 69 June 9, 2011 ...
Page 70
... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Dimensions in mm 16.0 0.3 8.0 0.1 1.75 0.1 7.5 0.1 +0.10/-0.00 1.55 +0.25/-0.00 1.50 4.0 0.1 2.0 0.1 6.5 0.1 10.3 0.1 2.1 0.1 0.30 0.05 13.3 0.1 70 June 9, 2011 ...
Page 71
... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 71 June 9, 2011 ...