HT48R30A HOLTEK [Holtek Semiconductor Inc], HT48R30A Datasheet

Page 1

... General Description The device is an 8-bit high performance RISC-like microcontroller designed for multi- ple I/O product applications. The device is par- ticularly suitable for use in products such as Rev. 1.10 HT48R30A-1 8-Bit Microcontroller 96´8 data memory RAM · Buzzer driving pair and PFD supported · ...

Page 2

... Block Diagram Rev. 1.10 HT48R30A-1 2 July 2, 2001 ...

Page 3

... PG0. The external interrupt input is activated on a high to low transition. Bidirectional I/O lines. Software instructions determine the PC0/TMR CMOS output or Schmitt trigger input with pull-high resistor I/O Pull-high* PC1~PC5 (determined by 1-bit pull-high options). The timer input are pin-shared with PC0. Rev. 1.10 HT48R30A-1 Description 3 July 2, 2001 ...

Page 4

... SYS f =8MHz 4.5 ¾ SYS 3.3V ¾ No load, f =4MHz SYS 5V ¾ 3.3V ¾ No load, f =4MHz SYS 5V ¾ No load, f =8MHz 5V ¾ SYS 3.3V ¾ No load, system HALT 5V ¾ 4 HT48R30A-1 Ta=25°C Typ. Max. Unit ¾ 5.5 V 5.5 V ¾ ¾ mA ¾ 10 ...

Page 5

... Without WDT 11 prescaler HT48R30A-1 Typ. Max. Unit ¾ ¾ ¾ mA ¾ 0.3V ¾ ¾ 0.4V ¾ ¾ ...

Page 6

... The conditional skip is activated by instruc- tions. Once the condition is met, the next in- struction during the c ur rent instruction execution, is discarded and a dummy cycle replaces it to get the proper in- struction. Otherwise proceed with the next in- struction. Execution flow 6 HT48R30A-1 t ¾ SYS ¾ ms ¾ ¾ ¾ ...

Page 7

... PC Program counter S10~S0: Stack register bits @7~@0: PCL bits 7 HT48R30A July 2, 2001 ...

Page 8

... (STATUS;0AH), interrupt control register Table Location * Table location P10~P8: Current program counter bits 8 HT48R30A July 2, 2001 ...

Page 9

... The RAM mapping Rev. 1.10 HT48R30A-1 general purpose data memory, addressed from 20H to 7FH, is used for data and control infor- mation under instruction commands. All of the data memory areas can handle arith- metic, logic, increment, decrement and rotate operations directly ...

Page 10

... If the stack is full, the interrupt request will not be acknowledged, even if the related in- terrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupts have a wake-up ca- pability interrupt is serviced, a control Function Status register 10 HT48R30A-1 July 2, 2001 ...

Page 11

... EMI, EEI, ETI are Function INTC register 11 HT48R30A-1 1 04H 2 08H July 2, 2001 ...

Page 12

... Even if the system enters the power down mode, the system clock is stopped, but the oscillator still works within a period of 72ms. The WDT oscilla- tor can be disabled by ROM code option to con- serve power. Watchdog Timer - WDT The WDT clock source is implemented by a ded- Watchdog Timer 12 HT48R30A-1 July 2, 2001 ...

Page 13

... Rev. 1.10 HT48R30A-1 WDTS register The WDT overflow under normal operation will initialize "chip reset" and set the status bit "TO". But in the HALT mode, the overflow will initialize a ²warm reset² and only the PC and SP are reset to zero. To clear the contents of WDT (including the WDT prescaler), three methods are adopted ...

Page 14

... Some registers remain unchanged during other reset conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining the PD and TO flags, the program can distinguish between different "chip resets". Rev. 1.10 HT48R30A RESET Conditions 0 0 RES reset during power-up u ...

Page 15

... Reset configuration Rev. 1.10 HT48R30A-1 The functional unit chip reset status are shown below. PC 000H Interrupt Disable Prescaler Clear Clear. After master reset, WDT WDT begins counting Timer/event Off Counter Input/output Input mode Ports Points to the top of SP the stack 15 July 2, 2001 ...

Page 16

... PG ---- -111 ---- -111 PGC ---- -111 ---- -111 Note: "*" stands for "warm reset" "u" stands for "unchanged" "x" stands for "unknown" Rev. 1.10 HT48R30A-1 RES Reset RES Reset (Normal Time-out (HALT) Operation) (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu ...

Page 17

... SYS RTC / SYS RTC / SYS RTC / /16 SYS RTC / /32 SYS RTC / /64 SYS RTC /128 or f /128 SYS RTC /256 or f /256 SYS RTC TMRC register Timer/Event Counter 17 HT48R30A-1 July 2, 2001 ...

Page 18

... To function as an input, the corresponding latch of the control register must write "1". The input source also depends on the control register. If the control register bit is "1", 18 HT48R30A-1 July 2, 2001 ...

Page 19

... PB0/PB1 are shown below ² data HT48R30A July 2, 2001 ...

Page 20

... The LVR uses the ²OR² function with the ex- ternal RES signal to perform chip reset. The relationship between V shown below. Note the voltage range for proper chip OPR operation at 4MHz system clock. 20 HT48R30A-1 and LVR July 2, 2001 ...

Page 21

... PA wake-up (By bit CMOS/SCHMITT input 6 PA, PB, PC, PG pull-high enable/disable (By port) 7 BZ/BZ enable/disable 8 LVR enable/disable System oscillator 9 Ext. RC, Ext.crystal, Int.RC+RTC or Int.RC+PG1/PG2 10 Int.RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz 11 Lock: unlock/lock Rev. 1.10 Low voltage reset Option /RTCOSC/disable TID or RTCOSC SYS 21 HT48R30A-1 July 2, 2001 ...

Page 22

... Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. Rev. 1.10 HT48R30A-1 Crystal or ceramic resonator for multiple I/O applications Note: C1=C2=300pF if f < ...

Page 23

... CPLA [m] Complement data memory with result in ACC Increment & Decrement INCA [m] Increment data memory with result in ACC INC [m] Increment data memory DECA [m] Decrement data memory with result in ACC DEC [m] Decrement data memory Rev. 1.10 HT48R30A-1 Instruction Cycle (1) ...

Page 24

... Skip if increment data memory is zero with result in ACC SDZA [m] Skip if decrement data memory is zero with result in ACC CALL addr Subroutine call RET Return from subroutine RET A,x Return from subroutine and load immediate data to ACC RETI Return from interrupt Rev. 1.10 HT48R30A-1 Instruction Cycle (1) 1 ...

Page 25

... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared. Otherwise the TO and PD flags remain unchanged. Rev. 1.10 HT48R30A-1 Instruction Cycle ( (1) 1 (1) ...

Page 26

... Rev. 1. ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö 26 HT48R30A-1 July 2, 2001 ...

Page 27

... Rev. 1. ¾ ¾ Ö Ö Ö Ö ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 27 HT48R30A-1 July 2, 2001 ...

Page 28

... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 28 HT48R30A-1 July 2, 2001 ...

Page 29

... Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] ¬ [m] Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 29 HT48R30A-1 July 2, 2001 ...

Page 30

... Data in the specified data memory is decremented by 1. Operation [m] ¬ [m]-1 Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ Ö ¾ ¾ 30 HT48R30A-1 July 2, 2001 ...

Page 31

... Rev. 1. ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 31 HT48R30A-1 July 2, 2001 ...

Page 32

... ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 32 HT48R30A-1 July 2, 2001 ...

Page 33

... Rev. 1. ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 33 HT48R30A-1 July 2, 2001 ...

Page 34

... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 34 HT48R30A-1 July 2, 2001 ...

Page 35

... Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ ¾ 35 HT48R30A-1 July 2, 2001 ...

Page 36

... ACC.7 ¬ ¬ [m].0 Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö 36 HT48R30A-1 July 2, 2001 ...

Page 37

... Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1) Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö ¾ ¾ ¾ ¾ ¾ ¾ 37 HT48R30A-1 July 2, 2001 ...

Page 38

... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 38 HT48R30A-1 July 2, 2001 ...

Page 39

... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Ö Ö Ö Ö ¾ ¾ Ö Ö Ö Ö 39 HT48R30A-1 July 2, 2001 ...

Page 40

... Rev. 1. ¾ ¾ Ö Ö Ö Ö ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 40 HT48R30A-1 July 2, 2001 ...

Page 41

... Rev. 1. ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 41 HT48R30A-1 July 2, 2001 ...

Page 42

... ACC ¬ ACC "XOR" x Affected flag(s) TC2 TC1 ¾ ¾ Rev. 1. ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ 42 HT48R30A-1 July 2, 2001 ...

Page 43

... Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 HT48R30A-1 43 July 2, 2001 ...